SAM4S16C Atmel Corporation, SAM4S16C Datasheet - Page 332
SAM4S16C
Manufacturer Part Number
SAM4S16C
Description
Manufacturer
Atmel Corporation
Specifications of SAM4S16C
Flash (kbytes)
1024 Kbytes
Pin Count
100
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
79
Ext Interrupts
79
Usb Transceiver
1
Quadrature Decoder Channels
2
Usb Speed
Full Speed
Usb Interface
Device
Spi
3
Twi (i2c)
2
Uart
4
Ssc
1
Sd / Emmc
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
1000
Analog Comparators
1
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
External Bus Interface
1
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.8/3.3
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
Pwm Channels
4
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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17.5.6
Name:
Address:
Access:
• SMEN: Supply Monitor Wake Up Enable
0 (NOT_ENABLE) = the supply monitor detection has no wake up effect.
1 (ENABLE) = the supply monitor detection forces the wake up of the core power supply.
• RTTEN: Real Time Timer Wake Up Enable
0 (NOT_ENABLE) = the RTT alarm signal has no wake up effect.
1 (ENABLE) = the RTT alarm signal forces the wake up of the core power supply.
• RTCEN: Real Time Clock Wake Up Enable
0 (NOT_ENABLE) = the RTC alarm signal has no wake up effect.
1 (ENABLE) = the RTC alarm signal forces the wake up of the core power supply.
• LPDBCEN0: Low power Debouncer ENable WKUP0
0 (NOT_ENABLE) = the WKUP0 input pin is not connected with low power debouncer.
1 (ENABLE) = the WKUP0 input pin is connected with low power debouncer and can force the a core wake up.
• LPDBCEN1: Low power Debouncer ENable WKUP1
0 (NOT_ENABLE) = the WKUP1input pin is not connected with low power debouncer.
1 (ENABLE) = the WKUP1 input pin is connected with low power debouncer and can force the a core wake up.
• LPDBCCLR: Low power Debouncer Clear
0 (NOT_ENABLE) = a low power debounce event does not create an immediate clear on half GPBR registers.
1 (ENABLE) = a low power debounce event on WKUP0 or WKUP1 generates an immediate clear on half GPBR registers.
332
332
LPDBCCLR
31
23
15
–
–
–
7
SAM4S
SAM4S
Supply Controller Wake Up Mode Register
SUPC_WUMR
0x400E141C
Read-write
LPDBCEN1
30
22
14
–
–
6
LPDBCEN0
WKUPDBC
29
21
13
–
–
5
28
20
12
–
–
4
–
RTCEN
27
19
11
–
–
–
3
RTTEN
26
18
10
–
–
2
LPDBC
SMEN
25
17
–
9
–
1
11100A–ATARM–28-Oct-11
11100A–ATARM–28-Oct-11
24
16
–
8
–
0
–
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