MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 105

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.16.2
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data.
Refer to
This section refers to registers and control bits only by their names.
4.16.2.1
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting
[SBR12:SBR0], first write to SCIBD (hi) to buffer the high half of the new value, and then write to SCIBD (lo). The working value
in SCIBD (hi) does not change until SCIBD (lo) is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or
transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
Note:
Note:
Freescale Semiconductor
Offset
Offset
91.
92.
Reset
Reset
RXEDGIE
SBR[128]
SBR[7:0]
W
W
LBKDIE
R
R
Field
Field
4:0
7:0
(91)
(92)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
7
6
Section 4.6, “Die to Die Interface - Target
0x40
0x41
LBKDIE
SBR7
Register Definition
LIN Break Detect Interrupt Enable (for LBKDIF)
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate
for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1
to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate
for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1
to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
SCI Baud Rate Registers (SCIBD (hi), SCIBD (lo))
7
0
7
0
0
1
0
1
Hardware interrupts from LBKDIF disabled (use polling).
Hardware interrupt requested when LBKDIF flag is 1.
Hardware interrupts from RXEDGIF disabled (use polling).
Hardware interrupt requested when RXEDGIF flag is 1.
RXEDGIE
SBR6
6
0
6
0
Table 134. SCI Baud Rate Register (SCIBD (hi))
Table 136. SCI Baud Rate Register (SCIBDL)
Table 135. SCIBD (hi) Field Descriptions
Table 137. SCIBDL Field Descriptions
SBR5
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
of this data sheet for the absolute address assignments for all SCI registers.
SBR12
SBR4
4
0
4
0
Description
Description
SBR11
SBR3
3
0
3
0
Table
Table
Serial Communication Interface (S08SCIV4)
137.
135.
SBR10
SBR2
2
0
2
1
SBR9
SBR1
1
0
1
0
Access: User read/write
Access: User read/write
SBR8
SBR0
0
0
0
0
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