MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 294

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.40
4.40.1
The module implements the following:
The Flash memory is ideal for single-supply applications allowing for field reprogramming without requiring external high voltage
sources for program or erase operations. The Flash module includes a memory controller that executes commands to modify
Flash memory contents. The user interface to the memory controller consists of the indexed Flash Common Command Object
(FCCOB) register which is written to with the command, global address, data, and any required command parameters. The
memory controller must complete the execution of a command before the FCCOB register can be written to with a new command.
The Flash memory may be read as bytes, aligned words, or misaligned words. Read access time is one bus cycle for bytes and
aligned words, and two bus cycles for misaligned words. For Flash memory, an erased bit reads 1 and a programmed bit reads 0.
It is possible to read from P-Flash memory while some commands are executing on D-Flash memory. It is not possible to read
from D-Flash memory while a command is executing on P-Flash memory. Simultaneous P-Flash and D-Flash operations are
discussed in
Both P-Flash and D-Flash memories are implemented with Error Correction Codes (ECC) that can resolve single bit faults and
detect double bit faults. For P-Flash memory, the ECC implementation requires that programming be done on an aligned 8 byte
basis (a Flash phrase). Since P-Flash memory is always read by half-phrase, only one single bit fault in an aligned 4 byte
half-phrase containing the byte or word accessed will be corrected.
4.40.1.1
Command Write Sequence — An MCU instruction sequence to execute built-in algorithms (including program and erase) on
the Flash memory.
D-Flash Memory — The D-Flash memory constitutes the nonvolatile memory store for data.
D-Flash Sector — The D-Flash sector is the smallest portion of the D-Flash memory that can be erased. The D-Flash sector
consists of four 64 byte rows for a total of 256 bytes.
NVM Command Mode — An NVM mode using the CPU to setup the FCCOB register to pass parameters required for Flash
command execution.
Phrase — An aligned group of four 16-bit words within the P-Flash memory. Each phrase includes two sets of aligned double
words with each set including 7 ECC bits for single bit fault correction and double bit fault detection within each double word.
P-Flash Memory — The P-Flash memory constitutes the main nonvolatile memory store for applications.
P-Flash Sector — The P-Flash sector is the smallest portion of the P-Flash memory that can be erased. Each P-Flash sector
contains 512 bytes.
Program IFR — Nonvolatile information register located in the P-Flash block that contains the Device ID, Version ID, and the
Program Once field.
4.40.1.2
4.40.1.2.1
4.40.1.2.2
Freescale Semiconductor
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Single bit fault correction and double bit fault detection within a 32-bit double word during read operations
Automated program and erase algorithm with verify and generation of ECC parity bits
Fast sector erase and phrase program operation
Ability to read the P-Flash memory while programming a word in the D-Flash memory
Flexible protection scheme to prevent accidental program or erase of P-Flash memory
Single bit fault correction and double bit fault detection within a word during read operations
kbytes of P-Flash (Program Flash) memory
kbytes of D-Flash (Data Flash) memory
64 KByte Flash Module (S12FTMRC64K1V1)
Section
Introduction
Glossary
Features
A Flash word or phrase must be in the erased state before being programmed. Cumulative
programming of bits within a Flash word or phrase is not allowed.
P-Flash Features
D-Flash Features
4.40.4.4.
MM912_634 Advance Information, Rev. 4.0
CAUTION
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