MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 122

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.19.3.3
This section consists of register descriptions in address order. Each description includes a standard register diagram with an
associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
4.19.3.3.1
4.19.3.3.2
Freescale Semiconductor
Note:
Note:
110.
Offset
111.
Note:
Offset
106.
107.
108.
109.
Reset
Reset
W
W
R
R
IOS[3-0]
Offset
(110)
Field
(111)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
3-0
0xCD
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Always read $00.
Only writable in special modes. (Refer to SOC Guide for different modes).
Write to these registers have no meaning or effect during input capture.
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
(106)
0xC0
0xC1
Register Descriptions
7
0
0
Input Capture or Output Compare Channel Configuration
7
0
0
Timer Input Capture/Output Compare Select (TIOS)
Timer Compare Force Register (CFORC)
0 - The corresponding channel acts as an input capture.
1 - The corresponding channel acts as an output compare.
Table 162. Timer Input Capture/Output Compare Select (TIOS)
6
0
0
6
0
0
Timer Input Capture/Output Compare Register 0 (TC0(hi))
Timer Input Capture/Output Compare Register 0 (TC0(lo))
Timer Input Capture/Output Compare Register 1 (TC1(hi))
Timer Input Capture/Output Compare Register 1 (TC1(lo))
Timer Input Capture/Output Compare Register 2 (TC2(hi))
Timer Input Capture/Output Compare Register 2 (TC2(lo))
Timer Input Capture/Output Compare Register 3 (TC3(hi))
Table 164. Timer Compare Force Register (CFORC)
Table 163. TIOS - Register Field Descriptions
Main Timer Interrupt Flag 2 (TFLG2)
MM912_634 Advance Information, Rev. 4.0
5
0
0
Table 161. Module Memory Map
5
0
0
Use
4
0
0
4
0
0
Description
FOC3
IOS3
3
0
3
0
0
Basic Timer Module - TIM (TIM16B4C)
FOC2
IOS2
2
0
2
0
0
FOC1
IOS1
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
1
0
1
0
0
Access: User read/write
Access: User read/write
Read/Write
Access
(109)
(108)
(108)
(108)
(108)
(108)
(108)
FOC0
IOS0
0
0
0
0
0
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