MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 170

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.29.3.2.4
Read: Anytime
Write: Anytime
These four index bits are used to map 16 kB blocks into the Flash page window located in the local (CPU or BDM) memory map
from address 0x8000 to address 0xBFFF (see
within the 6 kB Local map. The PPAGE index register is effectively used to construct paged Flash addresses in the Local map
format. The CPU has special access to read and write this register directly during execution of CALL and RTC instructions.
The fixed 16 kB page from 0x0000 to 0x3FFF is the page number 0x0C. Parts of this page are covered by Registers, D-Flash
and RAM space. See SoC Guide for details.
The fixed 16 kB page from 0x4000–0x7FFF is the page number 0x0D.
The reset value of 0x0E ensures that there is linear Flash space available between addresses 0x0000 and 0xFFFF out of reset.
The fixed 16 kB page from 0xC000-0xFFFF is the page number 0x0F.
4.29.4
The S12PMMC block performs several basic functions of the S12I sub-system operation: MCU operation modes, priority control,
address mapping, select signal generation and access limitations for the system. Each aspect is described in the following
subsections.
Freescale Semiconductor
Address: 0x0030
Reset
PIX[3:0]
W
R
Field
3–0
Functional Description
Program Page Index Bits 3–0 — These page index bits are used to select which of the 256 P-Flash or ROM array pages is to
be accessed in the Program Page Window.
7
0
0
Program Page Index Register (PPAGE)
Writes to this register using the special access of the CALL and RTC instructions will be
complete before the end of the instruction execution.
Bit17
6
0
0
PPAGE Register [3:0]
Table 252. Program Page Index Register (PPAGE)
Table 253. PPAGE Field Descriptions
MM912_634 Advance Information, Rev. 4.0
Figure 50. PAGE Address Mapping
5
0
0
Figure
Global Address [17:0]
50). This supports accessing up to 256 kB of Flash (in the Global map)
Bit14
NOTE
4
0
0
Bit13
Description
Address: CPU Local Address
PIX3
3
1
Address [13:0]
or BDM Local Address
PIX2
2
1
Bit0
PIX1
1
1
PIX0
0
0
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