MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 96

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.
If the channel is not enabled, then writes to the period and duty registers will go directly to the latches as well as the buffer.
A change in duty or period can be forced into effect “immediately” by writing the new value to the duty and/or period registers,
and then writing to the counter. This forces the counter to reset and the new duty and/or period values to be latched. In addition,
since the counter is readable, it is possible to know where the count is with respect to the duty value, and software can be used
to make adjustments
4.14.4.2.4
Each channel has a dedicated 8-bit up/down counter which runs at the rate of the selected clock source (see
“PWM Clock Select”
period register as shown in
causing the PWM waveform to also change state. A match between the PWM counter and the period register behaves differently
depending on what output mode is selected as shown in
and
Each channel counter can be read at anytime without affecting the count or the operation of the PWM channel.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of
both duty and period registers with values from the buffers, and the output to change according to the polarity bit. When the
channel is disabled (PWMEx = 0), the counter stops. When a channel becomes enabled (PWMEx = 1), the associated PWM
counter continues from the count in the PWMCNTx register. This allows the waveform to continue where it left off when the
channel is re-enabled. When the channel is disabled, writing “0” to the period register will cause the counter to reset on the next
selected clock.
Generally, writes to the counter are done prior to enabling a channel in order to start from a known state. However, writing a
counter can also be done while the PWM channel is enabled (counting). The effect is similar to writing the counter when the
channel is disabled, except that the new period is started immediately with the output set according to the polarity bit.
The counter is cleared at the end of the effective period (see
“Center Aligned Outputs”
4.14.4.2.5
The PWM timer provides the choice of two types of outputs, left aligned or center aligned. They are selected with the CAEx bits
in the PWMCTL register. If the CAEx bit is cleared (CAEx = 0), the corresponding PWM output will be left aligned.
In left aligned output mode, the 8-bit counter is configured as an up counter only. It compares to two registers, a duty register and
a period register as shown in the block diagram in
changes state causing the PWM waveform to also change state. A match between the PWM counter and the period register
resets the counter and the output flip-flop, as shown in
duty register to the associated registers, as described in
to the value in the period register – 1.
Freescale Semiconductor
When PWMCNTx register written to any value When PWM channel is enabled (PWMEx = 1).
Section 4.14.4.2.6, “Center Aligned
Counter Clears ($00)
Effective period ends
When forcing a new period or duty into effect immediately, an irregular PWM cycle can occur.
Depending on the polarity bit, the duty registers will contain the count of either the high time
or the low time.
PWM Timer Counters
To start a new “clean” PWM waveform without any “history” from the old waveform, writing
the channel counter (PWMCNTx) must happen prior to enabling the PWM channel
(PWMEx = 1).
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to
occur.
Left Aligned Outputs
for the available clock sources and rates). The counter compares to two registers, a duty register and a
for more details).
Figure
24. When the PWM counter matches the duty register, the output flip-flop changes state,
Outputs”.
Table 130. PWM Timer Counter Conditions
MM912_634 Advance Information, Rev. 4.0
Counts from last value in PWMCNTx.
Figure
Figure
Counter Counts
24. When the PWM counter matches the duty register the output flip-flop
Section 4.14.4.2.3, “PWM Period and
Figure 24
NOTE
NOTE
NOTE
Section 4.14.4.2.5, “Left Aligned Outputs”
24, as well as performing a load from the double buffer period and
and described in
Section 4.14.4.2.5, “Left Aligned Outputs”
When PWM channel is disabled (PWMEx = 0)
PWM Control Module (PWM8B2C)
Duty”. The counter counts from 0
Counter Stops
and
Section 4.14.4.2.6,
Section 4.14.4.1,
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