MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 136

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.20.4.2
4.20.4.2.1
Freescale Semiconductor
Note:
127.
ADR15 (hi)
ADR15 (lo)
Offset
Offset
Note:
128.
Register /
4 - ADCRST
Reset
0xA4
0xA5
7 - SCIE
5 - OCE
W
6 - CCE
PS2…0
R
Field
(128)
2-0
(127)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
0x80
W
W
R
R
SCIE
Register Definition
Sequence Complete Interrupt Enable
Continuous Conversion Enable
Offset Compensation Enable
Analog Digital Converter RESET
ADC Clock Prescaler Select (D2DCLK to ADCCLK divider)
7
0
ADC Config Register (ACR)
Bit 7
0 - Sequence Complete Interrupt Disabled
1 - Sequence Complete Interrupt Enabled
0 - Continuous Conversion Disabled
1 - Continuous Conversion Enabled
0 - Offset Compensation Disabled
1 - Offset Compensation Enabled. This feature requires the CH15 bit in the ADC Conversion Control Register (ACCR)
to be set for all conversions
0 - Analog Digital Converter in Normal Operation
1 - Analog Digital Converter in Reset Mode. All ADC registers will reset to initial values. The bit has to be cleared to allow
ADC operation
000 - 10
001 - 8
010 - 6
011 - 4
100 - 2
101 - 1
110 - 1
111 - 1
ADR15[1:0]
CCE
6
0
Table 198. Analog Digital Converter Module - Memory Map
6
Table 200. ACR - Register Field Descriptions
Table 199. ADC Config Register (ACR)
MM912_634 Advance Information, Rev. 4.0
OCE
5
0
5
ADCRST
4
0
4
Description
ADR15[9:2]
3
0
0
3
PS2
2
0
2
PS1
1
0
Access: User read/write
1
PS0
Bit 0
0
0
136