MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 129

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.19.3.3.14
Freescale Semiconductor
Note:
Note:
124.
123.
Offset
Offset
Reset
Reset
Reset
Reset
W
W
R
R
W
W
R
R
Field
(124)
TOF
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(123)
7
0xD0, 0xD1
0xCE, 0xCF
tc1_15
tc1_7
tc0_15
tc0_7
15
Timer Overflow Flag
0
7
0
The TFLG2 register indicates when an interrupt has occurred. Writing a one to the TOF bit
will clear it. Any access to TCNT will clear TOF bit of TFLG2 register if the TFFCA bit in
TSCR register is set.
Timer Input Capture/Output Compare Registers (TC3 - TC0)
15
0
7
0
1 = Indicates that an Interrupt has occurred (Set when 16-bit free-running timer counter overflows from $FFFF to
$0000)
0 = Flag indicates an Interrupt has not occurred.
Table 191. Timer Input Capture/Output Compare Register 0 (TC0)
Table 192. Timer Input Capture/Output Compare Register 1(TC1)
tc1_14
tc1_6
tc0_14
tc0_6
14
0
6
0
14
0
6
0
Table 190. TFLG2 - Register Field Descriptions
tc1_13
MM912_634 Advance Information, Rev. 4.0
tc1_5
tc0_13
tc0_5
13
0
5
0
13
0
5
0
tc1_12
tc0_12
tc1_4
tc0_4
NOTE
12
12
0
4
0
0
4
0
Description
tc1_11
tc0_11
tc1_3
tc0_3
11
11
0
3
0
0
3
0
Access: User read(anytime)/write (special mode)
Access: User read(anytime)/write (special mode)
Basic Timer Module - TIM (TIM16B4C)
tc1_10
tc0_10
tc1_2
tc0_2
10
10
0
2
0
0
0
2
tc0_9
tc0_1
tc1_9
tc1_1
9
0
1
0
9
0
1
0
tc0_8
tc0_0
tc1_8
tc1_0
8
0
0
0
8
0
0
0
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