MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 177

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.30
4.30.1
The INT module decodes the priority of all system exception requests and provides the applicable vector for processing the
exception to the CPU. The INT module supports:
Each of the I bit maskable interrupt requests is assigned to a fixed priority level.
4.30.1.1
Table 255
4.30.1.2
Note:
4.30.1.3
4.30.1.4
Figure 55
Freescale Semiconductor
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The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used as upper
byte) and 0x00 (used as lower byte).
I bit and X bit maskable interrupt requests
A non-maskable unimplemented op-code trap
A non-maskable software interrupt (SWI) or background debug mode request
Three system reset vector requests
A spurious interrupt vector
Interrupt vector base register (IVBR)
One spurious interrupt vector (at address vector base
2–58 I bit maskable interrupt vector requests (at addresses vector base + 0x0082–0x00F2).
I bit maskable interrupts can be nested.
One X bit maskable interrupt vector request (at address vector base + 0x00F4).
One non-maskable software interrupt request (SWI) or background debug mode vector request (at address vector base
+ 0x00F6).
One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).
Three system reset vectors (at addresses 0xFFFA–0xFFFE).
Determines the highest priority interrupt vector requests, drives the vector to the bus on CPU request
Wakes up the system from stop mode when an appropriate interrupt request occurs.
Run mode
This is the basic mode of operation.
Stop Mode
In stop mode, the clock to the INT module is disabled. The INT module is however capable of waking-up the CPU from
stop mode if an interrupt occurs. Please refer to
Freeze mode (BDM active)
In freeze mode (BDM active), the interrupt vector base register is overridden internally. Please refer to
Section 4.30.3.1.1, “Interrupt Vector Base Register (IVBR)”
shows a block diagram of the INT module.
contains terms and abbreviations used in the document.
Interrupt Module (S12SINTV1)
Introduction
Glossary
Features
Modes of Operation
Block Diagram
Term
MCU
CCR
ISR
MM912_634 Advance Information, Rev. 4.0
Table 255. Terminology
Condition Code Register (in the CPU)
Interrupt Service Routine
Micro-Controller Unit
Section 4.30.5.3, “Wake-up from Stop Mode”
(160)
+ 0x0080).
for details.
Meaning
for details.
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