MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 97

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

To calculate the output frequency in left aligned output mode for a particular channel, take the selected clock source frequency
for the channel (A, B, SA, or SB), and divide it by the value in the period register for that channel.
As an example of a left aligned output, consider the following case:
The output waveform generated is shown in
4.14.4.2.6
For a center aligned output mode selection, set the CAEx bit (CAEx = 1) in the PWMCTL register, and the corresponding PWM
output will be center aligned.
The 8-bit counter operates as an up/down counter in this mode, and is set to up whenever the counter is equal to $00. The counter
compares to two registers, a duty register and a period register, as shown in the block diagram in
counter matches the duty register, the output flip-flop changes state, causing the PWM waveform to also change state. A match
between the PWM counter and the period register changes the counter direction from an up-count to a down-count. When the
PWM counter decrements and matches the duty register again, the output flip-flop changes state, causing the PWM output to
also change state. When the PWM counter decrements and reaches zero, the counter direction changes from a down-count back
to an up-count, and a load from the double buffer period and duty registers to the associated registers is performed, as described
Freescale Semiconductor
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PWMx Frequency = Clock (A, B, SA, or SB) / PWMPERx
PWMx Duty Cycle (high time as a % of period):
— Polarity = 0 (PPOLx = 0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
— Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Clock Source = E, where E = 10 kHz (100 µs period)
PWMx Frequency = 10 kHz/4 = 2.5 kHz
PWMx Period = 400 µs
PWMx Duty Cycle = 3/4 *100% = 75%
PPOLx = 0
PWMPERx = 4
PWMDTYx = 1
Changing the PWM output mode from left aligned to center aligned output (or vice versa)
while channels are operating can cause irregularities in the PWM output. It is recommended
to program the output mode before enabling the PWM channel.
Center Aligned Outputs
PPOLx = 0
PPOLx = 1
E = 100 µs
Figure 26. PWM Left Aligned Output Example Waveform
Figure 25. PWM Left Aligned Output Waveform
Figure
MM912_634 Advance Information, Rev. 4.0
PWMDTYx
Period = 400 µs
26.
Duty Cycle = 75%
NOTE
Period = PWMPERx
PWM Control Module (PWM8B2C)
Figure
24. When the PWM
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