MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 252

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Read: Anytime
Write: Only in Special Mode
Freescale Semiconductor
cpmu_test_gfe
cpmu_test_xfc
0x003D
test_sqw_osc
fmcs_reg_sel
fc_force_en
Reset
W
vcofrq2
fm_test
R
Field
_en
7
6
5
4
3
1
0
fmcs_reg_se
FMCS Register Select Bit— This bit switches either CPMUTEST1 or CPMUFMCS test register to address 0x003E.
0 CPMUTEST1 register is visible on address 0x003E, fm_cs[7:0] of hardmacro driven dynamically (triangular)
1 CPMUFMCS register is visible on address 0x003E, fm_cs[7:0] of hardmacro driven to value of FMCS register.
Glitch Filter Enable Test Bit — This bit goes to the PTI controller, it is intended to enable the RESET pad glitch filter in
functional test mode (where it is by default disabled).
0 Glitch Filter disable request
1 Glitch Filter enable request
XFC Test Pin Enable — This bit routes the external XFC test pin to the internal filter node. Using this test feature make sure
that only one source is driving the internal filter node (FC). So for this case write fc_force_en=0, pfd_force_en=1,
pfd_force_up=pfd_force_down=0.
0 external XFC test pin not connected to internal filter node
1 external XFC test pin connected to internal filter node
FC Force Enable Bit — This bit allows to force the internal filter node FC to defined values. If fc_force_en=1, REFFRQ[1] bit
(in CPMUREFDIV register) selects either 1/2 or 1/3 V
that only one source is driving the internal filter node (FC). So for this case write cpmu_test_xfc_en=0, pfd_force_en=1,
pfd_force_up=pfd_force_down=0.
0 Internal filter node (FC) not driven from defined values (1/2 or 1/3 V
1 If REFFRQ[1]=1 then internal filter node (FC) is driven to V
VCO gain Bit 2 — This bit selects together with the VCOFRQ[1:0] bits of the CPMUSYNR register the gain of the VtoI
converter in the PLL. Setting vcofrq2-0 all to 1 is intended for 160MHz VCOCLK generation.
FM test amplitude Bit — This bit multiplies FM amplitude determined by FM1,FM0 and CPMUFMCS[7:0] by 4. This is to
amplify frequency variation on VCOCLK when using PLL test modes (pfd_force_en, fc_force_en). A higher frequency variation
is easier to measure on tester.
0 FM amplitude multiplied by 1
1 FM amplitude multiplied by 4
Test square wave enable Bit — Enables XTAL pin digital input data used for Oscillator test.
0 XTAL pin as digital input disabled
1 XTAL pin as digital input enabled
l
7
0
0
if fm_enable=1.
If REFFRQ[1]=0 then internal filter node (FC) is driven to V
cpmu_test_
Note 1
gfe
6
= Unimplemented or Reserved
0
0
Table 359. Reserved Register (CPMUTEST0)
cpmu_test_x
Table 360. CPMUTEST0 Field Descriptions
fc_en
MM912_634 Advance Information, Rev. 4.0
5
0
1) Power on reset clears the crg_test_gfe bit
0
fc_force_en
4
0
DDPLL
Description
0
voltage to be driven on FC node. Using this test feature make sure
vcofrq2
3
0
DDPLL
DDPLL
0
/3.
/2.
DDPLL
2
0
0
)
fm_test
1
0
0
test_sqw_o
sc
0
0
0
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