MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 91

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

For boundary case programming values, please refer to
Note:
4.14.3.7
There is a dedicated duty register for each channel. The value in this register determines the duty of the associated PWM
channel. The duty value is compared to the counter and if it is equal to the counter value a match occurs and the output changes
state.
The duty registers for each channel are double buffered, so if they change while the channel is enabled, the change will NOT
take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old duty waveform or the new duty waveform, not some variation in
between. If the channel is not enabled, then writes to the duty register will go directly to the latches as well as the buffer.
See
To calculate the output duty cycle (high time as a% of period) for a particular channel:
For boundary case programming values, please refer to
Note:
Freescale Semiconductor
Offset
Offset
87.
88.
Reset
Reset
W
W
R
R
•
•
•
•
•
•
•
•
Section 4.14.4.2.3, “PWM Period and Duty”
(87)
(88)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Left aligned output (CAEx = 0)
PWMx Period = Channel Clock Period * PWMPERx Center Aligned Output (CAEx = 1)
PWMx Period = Channel Clock Period * (2 * PWMPERx)
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
Polarity = 0 (PPOL x =0)
Polarity = 1 (PPOLx = 1)
0x66/0x67
0x68/0x69
– Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
– Duty Cycle = [PWMDTYx / PWMPERx] * 100%
Bit 7
Bit 7
PWM Channel Duty Registers (PWMDTYx)
7
0
7
0
Reads of this register return the most recent value written. Reads do not necessarily return
the value of the currently active duty due to the double buffering scheme.
Depending on the polarity bit, the duty registers will contain the count of either the high time
or the low time. If the polarity bit is one, the output starts high and then goes low when the
duty count is reached, so the duty registers contain a count of the high time. If the polarity
bit is zero, the output starts low and then goes high when the duty count is reached, so the
duty registers contain a count of the low time.
6
0
6
0
6
6
Table 128. PWM Channel Period Registers (PWMPERx)
Table 129. PWM Channel Duty Registers (PWMDTYx)
MM912_634 Advance Information, Rev. 4.0
5
0
5
0
5
5
for more information.
Section 4.14.4.2.7, “PWM Boundary
Section 4.14.4.2.7, “PWM Boundary
NOTE
NOTE
4
0
4
0
4
4
3
0
3
0
3
3
2
0
2
0
2
2
PWM Control Module (PWM8B2C)
Cases”.
Cases”.
1
0
1
0
1
1
Access: User read/write
Access: User read/write
Bit 0
Bit 0
0
0
0
0
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