MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 181

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.31
4.31.1
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented in on-chip hardware
for minimal CPU intervention. All interfacing with the BDM is done via the BKGD pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while allowing more flexibility in
clock rates. This includes a sync signal to determine the communication rate and a handshake signal to indicate when an
operation is complete. The system is backwards compatible to the BDM of the S12 family with the following exceptions:
4.31.1.1
The BDM includes these distinctive features:
4.31.1.2
BDM is available in all operating modes but must be enabled before firmware commands are executed. Some systems may have
a control bit that allows suspending the function during background debug mode.
4.31.1.2.1
All of these operations refer to the part in run mode and not being secured. The BDM does not provide controls to conserve power
during run mode.
4.31.1.2.2
If the device is in secure mode, the operation of the BDM is reduced to a small subset of its regular run mode operation. Secure
operation prevents access to Flash other than allowing erasure. For more information please see
4.31.1.2.3
The BDM can be used until stop mode is entered. The CPU cannot enter stop mode during BDM active mode.
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TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modified
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM (value for devices with HCS12S core is
0xC2)
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
Single-wire communication with host development system
Enhanced capability for allowing more flexibility in clock rates
SYNC command to determine communication rate
GO_UNTIL(171) command
Hardware handshake protocol to increase the performance of the serial communication
Active out of reset in special single chip mode
Nine hardware commands using free cycles, if available, for minimal CPU intervention
Hardware commands not requiring active BDM
14 firmware commands execute from the standard BDM firmware lookup table
When secured, hardware commands are allowed to access the register space in special single chip mode, if the Flash
erase tests fail.
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM (value for devices with HCS12S core is
0xC2)
BDM hardware commands are operational until system stop mode is entered
Normal modes
General operation of the BDM is available and operates the same in all normal modes.
Special single chip mode
In special single chip mode, background operation is enabled and active out of reset.This allows programming a system
with blank memory.
Background Debug Module (S12SBDMV1)
Introduction
Features
Modes of Operation
Regular Run Modes
Secure Mode Operation
Low-power Modes
MM912_634 Advance Information, Rev. 4.0
Section 4.31.4.1,
“Security”.
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