MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 145

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.26
A trimming option is implemented to increase some device parameter accuracy. As the MM912_634 analog die is
exclusively combined with a FLASH- MCU, the required trimming values can be calculated during the final test of
the device, and stored to a fixed position in the FLASH memory. During start-up of the system, the trimming values
have to be copied into the MM912_634 analog die trimming registers.
The trimming registers will maintain their content during Low Power mode, Reset will set the default value.
4.26.1
4.26.1.1
There are four trimming registers implemented (CTR0…CTR3), with CTR2 being reserved for future use. The following table
shows the registers used.
At system startup, the trimming information have to be copied from the MCU IFR Flash location to the corresponding MM912_634
analog die trimming registers. The following table shows the register correlation.
Freescale Semiconductor
Note:
Offset
137.
0xF0
0xF1
0xF2
0xF3
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Trimming Reg 0
Trimming Reg 1
Trimming Reg 2
Trimming Reg 3
Note:
138.
MM912_634 - Analog Die Trimming
Memory Map and Register Definition
Name
CTR0
CTR1
CTR2
CTR3
Module Memory Map
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Two word (16-Bit) transfers including CTR2 are recommended at system startup. The IFR
register has to be enabled for reading
(MMCCTL1))
To trim the bg1p25sleep there is two steps:
Step 1: First choose the right trim step by adjusting SLPBGTR[2:0] with SLPBGTRE=1,
SLPBG_LOCK bit has to stay at 0.
Step 2: Once the trim value is known, correct SLPBGTR[2:0], SLPBGTRE and
SLPBG_LOCK bits have to be set at the same time to apply and lock the trim. Once the trim
is locked, no other trim on the parameter is possible.
Name
CTR0
CTR1
CTR2
CTR3
Table 213. MM912_634 - MCU vs. Analog Die Trimming Register Correlation
W
W
W
W
R
R
R
R
OFFCTR
Table 212. MM912_634 Analog Die Trimming Registers
LINTRE
BGTRE
E
7
0
OFFCTR
MM912_634 Advance Information, Rev. 4.0
CTR1_6
LINTR
MCU IFR Address
6
0
2
0x4C
0x4D
0x4E
0x4F
BGTRIMU
OFFCTR1
WDCTRE
(Section 4.29.3.2.3, “MMC Control Register
P
5
0
NOTE
NOTE
SLPBGTR
BGTRIMD
OFFCTR0
CTR0_4
N
E
4
SLPBG_LOC
IREFTRE
CTR3_E
CTR0_3
K
3
Analog Offset
MM912_634 - Analog Die Trimming
SLPBGTR
WDCTR2
IREFTR2
CTR3_2
0xF0
0xF1
0xF2
0xF3
2
2
(138)
SLPBGTR
WDCTR1
IREFTR1
CTR3_1
1
1
SLPBGTR
WDCTR0
MCU
IREFTR0
CTR3_0
ANALOG
0
0
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