MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 217

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.4.2.2
Using the AB comparator pair for a range comparison, the data bus can also be used for qualification by using the comparator A
data registers. Furthermore the DBGACTL RW and RWE bits can be used to qualify the range comparison on either a read or a
write access. The corresponding DBGBCTL bits are ignored. The SZE and SZ control bits are ignored in range mode. The
comparator A TAG bit is used to tag range comparisons. The comparator B TAG bit is ignored in range modes. In order for a
range comparison using comparators A and B, both COMPEA and COMPEB must be set; to disable range comparisons both
must be cleared. The comparator A BRK bit is used to for the AB range, the comparator B BRK bit is ignored in range mode.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
4.32.4.2.2.1
In the Inside Range comparator mode, comparator pair A and B can be configured for range comparisons. This configuration
depends upon the control register (DBGC2). The match condition requires that a valid match for both comparators happens on
the same bus cycle. A match condition on only one comparator is not valid. An aligned word access which straddles the range
boundary is valid only if the aligned address is inside the range.
4.32.4.2.2.2
In the Outside Range comparator mode, comparator pair A and B can be configured for range comparisons. A single match
condition on either of the comparators is recognized as valid. An aligned word access which straddles the range boundary is valid
only if the aligned address is outside the range.
Outside range mode in combination with tagging can be used to detect if the opcode fetches are from an unexpected range. In
forced match mode the outside range match would typically be activated at any interrupt vector fetch or register access. This can
be avoided by setting the upper range limit to $3FFFF or lower range limit to $00000 respectively.
4.32.4.3
Match modes are used as qualifiers for a state sequencer change of state. The Comparator control register TAG bits select the
match mode. The modes are described in the following sections.
4.32.4.3.1
When configured for forced matching, a comparator channel match can immediately initiate a transition to the next state
sequencer state whereby the corresponding flags in DBGSR are set. The state control register for the current state determines
the next state. Forced matches are typically generated 2-3 bus cycles after the final matching address bus cycle, independent of
comparator RWE/RW settings. Furthermore since opcode fetches occur several cycles before the opcode execution a forced
match of an opcode address typically precedes a tagged match at the same address.
4.32.4.3.2
If a CPU taghit occurs a transition to another state sequencer state is initiated and the corresponding DBGSR flags are set. For
a comparator related taghit to occur, the DBG must first attach tags to instructions as they are fetched from memory. When the
tagged instruction reaches the execution stage of the instruction queue a taghit is generated by the CPU. This can initiate a state
sequencer transition.
4.32.4.3.3
Independent of comparator matches it is possible to initiate a tracing session and/or breakpoint by writing to the TRIG bit in
DBGC1. If configured for begin aligned tracing, this triggers the state sequencer into the Final State, if configured for end
alignment, setting the TRIG bit disarms the module, ending the session and issues a forced breakpoint request to the CPU.
Freescale Semiconductor
NDB
Match Modes (Forced or Tagged)
0
0
1
1
Range Comparisons
Inside Range (CompA_Addr  Address  CompB_Addr)
Outside Range (address < CompA_Addr or Address > CompB_Addr)
Forced Match
Tagged Match
Immediate Trigger
DBGADHM[n] /
DBGADLM[n]
0
1
0
1
Table 322. NDB and MASK Bit Dependency
MM912_634 Advance Information, Rev. 4.0
Compare data bus bit. Match on equivalence.
Compare data bus bit. Match on difference.
Do not compare data bus bit.
Do not compare data bus bit.
Comment
217