MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 220

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MARK1
MARK2
SUB_1
ADDR1
IRQ_ISR
MARK1
IRQ_ISR
SUB_1
ADDR1
4.32.4.5.2.2
Loop1 Mode, similarly to Normal Mode also stores only COF address information to the trace buffer, it however allows the filtering
out of redundant information.
The intent of Loop1 Mode is to prevent the Trace Buffer from being filled entirely with duplicate information from a looping
construct such as delays using the DBNE instruction or polling loops using BRSET/BRCLR instructions. Immediately after
address information is placed in the Trace Buffer, the DBG module writes this value into a background register. This prevents
consecutive duplicate address entries in the Trace Buffer resulting from repeated branches.
Loop1 Mode only inhibits consecutive duplicate source address entries that would typically be stored in most tight looping
constructs. It does not inhibit repeated entries of destination addresses or vector addresses, since repeated entries of these
would most likely indicate a bug in the user’s code that the DBG module is designed to help find.
4.32.4.5.2.3
In Detail Mode, address and data for all memory and register accesses is stored in the trace buffer. This mode is intended to
supply additional information on indexed, indirect addressing modes where storing only the destination address would not
provide all information required for a user to determine where the code is in error. This mode also features information bit storage
to the trace buffer, for each address byte storage. The information bits indicate the size of access (word or byte) and the type of
access (read or write).
When tracing in Detail Mode, all cycles are traced except those when the CPU is either in a free or opcode fetch cycle.
4.32.4.5.2.4
In Compressed Pure PC Mode, the PC addresses of all executed opcodes, including illegal opcodes are stored. A compressed
storage format is used to increase the effective depth of the trace buffer. This is achieved by storing the lower order bits each
time and using 2 information bits to indicate if a 64 byte boundary has been crossed, in which case the full PC is stored.
Each Trace Buffer row consists of 2 information bits and 18 PC address bits
Freescale Semiconductor
LDX
JMP
NOP
BRN
NOP
DBNE
LDAB
STAB
RTI
LDX
JMP
LDAB
STAB
RTI
BRN
NOP
DBNE
In the following example an IRQ interrupt occurs during execution of the indexed JMP at
address MARK1. The BRN at the destination (SUB_1) is not executed until after the IRQ
service routine but the destination address is entered into the trace buffer to indicate that the
indexed JMP COF has taken place.
The execution flow taking into account the IRQ is as follows
Loop1 Mode
Detail Mode
Compressed Pure PC Mode
#SUB_1
0,X
*
A,PART5
#$F0
VAR_C1
#SUB_1
0,X
#$F0
VAR_C1
*
A,PART5
MM912_634 Advance Information, Rev. 4.0
; IRQ interrupt occurs during execution of this
;
; JMP Destination address TRACE BUFFER ENTRY 1
; RTI Destination address TRACE BUFFER ENTRY 3
;
; Source address TRACE BUFFER ENTRY 4
; IRQ Vector $FFF2 = TRACE BUFFER ENTRY 2
;
;
;
;
;
;
220