MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 335

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.41.4.2.1
When writing to the address window associated with blocking transactions, the CPU is held until the transaction is completed,
before completing the instruction.
following example.
Blocking writes should be used when clearing interrupt flags located in the target or other writes which require that the operation
at the target is completed before proceeding with the CPU instruction stream.
4.41.4.3
When writing to the address window associated with non-blocking transactions, the CPU can continue before the transaction is
completed. However if there was a transaction ongoing when doing the 2nd write the CPU is held until the first one is completed,
before executing the 2nd one.
example.
As the figure illustrates non-blocking writes have a performance advantage, but care must be taken that the following instructions
are not affected by the change in the target caused by the previous transaction.
4.41.4.4
When reading from the address window associated with blocking transactions, the CPU is held until the data is returned from the
target, before completing the
following example.
Freescale Semiconductor
Blocking
Write
Non-Blocking
Write
Blocking
Read
STAA
LDAA
STAA
NOP
STAA
LDAA
STAA
NOP
LDAA
STAA
LDAA
D2D activity
CPU activity
D2D activity
CPU activity
D2D activity
CPU activity
Non-Blocking Writes
Blocking Read
Blocking Writes
BLK_WINDOW+OFFS0 ; WRITE0 8-bit as a blocking transaction
#BYTE1
BLK_WINDOW+OFFS1 ; WRITE1 is executed after WRITE0 transaction is completed
NONBLK_WINDOW+OFFS0; write 8-bit as a non blocking transaction
#BYTE1
NONBLK_WINDOW+OFFS1; executed right after the first
BLK_WINDOW+OFFS0 ; Read 8-bit as a blocking transaction
MEM
BLK_WINDOW+OFFS1 ; Read 8-bit as a blocking transaction
instruction.Figure 119
STAA 0
STAA 0 LDAA # STAA 1
LDAA 0
Figure 119
Figure 119
Figure 119. Blocking and Non-Blocking Transfers.
shows the behavior of the CPU for a blocking write transaction shown in the following
Write Transaction 0
Write Transaction 0
MM912_634 Advance Information, Rev. 4.0
shows the behavior of the CPU for a blocking write transaction shown in the
Transaction 0
CPU Halted
CPU Halted
; load next byte
; Store result to local Memory
shows the behavior of the CPU for a blocking read transaction shown in the
Halted
CPU
LDAA # STAA 1
STAA
MEM
NOP
Write Transaction 1
LDAA 1
Write Transaction 1
Transaction 1
CPU Halted
CPU Halted
NOP
NOP
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