MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 114

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

In the case of a framing error, the receiver is inhibited from receiving any new characters until the framing error flag is cleared.
The receive shift register continues to function, but a complete character cannot transfer to the receive data buffer if FE is still set.
4.16.3.3.2
Receiver wake-up is a hardware mechanism that allows an SCI receiver to ignore the characters in a message that is intended
for a different SCI receiver. In such a system, all receivers evaluate the first character(s) of each message, and as soon as they
determine the message is intended for a different receiver, they write logic 1 to the receiver wake up (RWU) control bit in SCIC2.
When RWU bit is set, the status flags associated with the receiver (with the exception of the idle bit, IDLE, when RWUID bit is
set) are inhibited from setting, thus eliminating the software overhead for handling the unimportant message characters. At the
end of a message, or at the beginning of the next message, all receivers automatically force RWU to 0 so all receivers wake up
in time to look at the first character(s) of the next message.
4.16.3.3.2.1
When WAKE = 0, the receiver is configured for idle-line wake-up. In this mode, RWU is cleared automatically when the receiver
detects a full character time of the idle-line level. The M control bit selects 8-bit or 9-bit data mode that determines how many bit
times of idle are needed to constitute a full character time (10 or 11 bit times because of the start and stop bits).
When RWU is one and RWUID is zero, the idle condition that wakes up the receiver does not set the IDLE flag. The receiver
wakes up and waits for the first data character of the next message which will set the RDRF flag and generate an interrupt if
enabled. When RWUID is one, any idle condition sets the IDLE flag and generates an interrupt if enabled, regardless of whether
RWU is zero or one.
The idle-line type (ILT) control bit selects one of two ways to detect an idle line. When ILT = 0, the idle bit counter starts after the
start bit so the stop bit and any logic 1s at the end of a character count toward the full character time of idle. When ILT = 1, the
idle bit counter does not start until after a stop bit time, so the idle detection is not affected by the data in the last character of the
previous message.
4.16.3.3.2.2
When WAKE = 1, the receiver is configured for address-mark wake-up. In this mode, RWU is cleared automatically when the
receiver detects a logic 1 in the most significant bit of a received character (eighth bit in M = 0 mode and ninth bit in M = 1 mode).
Address-mark wake-up allows messages to contain idle characters but requires that the MSB be reserved for use in address
frames. The logic 1 MSB of an address frame clears the RWU bit before the stop bit is received and sets the RDRF flag. In this
case the character with the MSB set is received even though the receiver was sleeping during most of this character time.
4.16.3.4
The SCI system has three separate interrupt vectors to reduce the amount of software needed to isolate the cause of the
interrupt. One interrupt vector is associated with the transmitter for TDRE and TC events. Another interrupt vector is associated
with the receiver for RDRF, IDLE, RXEDGIF and LBKDIF events, and a third vector is used for OR, NF, FE, and PF error
conditions. Each of these ten interrupt sources can be separately masked by local interrupt enable masks. The flags can still be
polled by software when the local masks are cleared to disable generation of hardware interrupt requests.
The SCI transmitter has two status flags that optionally can generate hardware interrupt requests. Transmit data register empty
(TDRE) indicates when there is room in the transmit data buffer to write another transmit character to SCID. If the transmit
interrupt enable (TIE) bit is set, a hardware interrupt will be requested whenever TDRE = 1. Transmit complete (TC) indicates
that the transmitter is finished transmitting all data, preamble, and break characters and is idle with TxD at the inactive level. This
flag is often used in systems with modems to determine when it is safe to turn off the modem. If the transmit complete interrupt
enable (TCIE) bit is set, a hardware interrupt will be requested whenever TC = 1. Instead of hardware interrupts, software polling
may be used to monitor the TDRE and TC status flags if the corresponding TIE or TCIE local interrupt masks are 0s.
When a program detects that the receive data register is full (RDRF = 1), it gets the data from the receive data register by reading
SCID. The RDRF flag is cleared by reading SCIS1 while RDRF = 1 and then reading SCID.
When polling is used, this sequence is naturally satisfied in the normal course of the user program. If hardware interrupts are
used, SCIS1 must be read in the interrupt service routine (ISR). Normally, this is done in the ISR anyway to check for receive
errors, so the sequence is automatically satisfied.
The IDLE status flag includes logic that prevents it from getting set repeatedly when the RxD line remains idle for an extended
period of time. IDLE is cleared by reading SCIS1 while IDLE = 1 and then reading SCID. After IDLE has been cleared, it cannot
become set again until the receiver has received at least one new character and has set RDRF.
Freescale Semiconductor
Interrupts and Status Flags
Receiver Wake-up Operation
Idle-line Wake-up
Address-Mark Wake-up
MM912_634 Advance Information, Rev. 4.0
Serial Communication Interface (S08SCIV4)
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