MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 108

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.16.2.4
This register has eight read-only status flags. Writes have no effect. Special software sequences (which do not involve writing to
this register) are used to clear these status flags.
Note:
Freescale Semiconductor
Offset
95.
Reset
W
R
RDRF
TDRE
Field
RWU
Field
SBK
TC
(95)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
1
0
7
6
5
0x44
TDRE
Receiver Wake-up Control — This bit can be written to 1 to place the SCI receiver in a standby state where it waits for automatic
hardware detection of a selected wake-up condition. The wake-up condition is either an idle line between messages
(WAKE = 0, idle-line wake-up), or a logic 1 in the most significant data bit in a character (WAKE = 1, address-mark wake-up).
Application software sets RWU and (normally) a selected hardware condition automatically clears RWU. Refer to
Section 4.16.3.3.2, “Receiver Wake-up
Send Break — Writing a 1 and then a 0 to SBK queues a break character in the transmit data stream. Additional break
characters of 10 or 11 (13 or 14 if BRK13 = 1) bit times of logic 0 are queued as long as SBK = 1. Depending on the timing of
the set and clear of SBK relative to the information currently being transmitted, a second break character may be queued
before software clears SBK. Refer to
Transmit Data Register Empty Flag — TDRE is set out of reset and when a transmit data value transfers from the transmit data
buffer to the transmit shifter, leaving room for a new character in the buffer. To clear TDRE, read SCIS1 with TDRE = 1 and
then write to the SCI data register (SCID).
Transmission Complete Flag — TC is set out of reset and when TDRE = 1 and no data, preamble, or break character is being
transmitted.
TC is cleared automatically by reading SCIS1 with TC = 1 and then doing one of the following three things:
Receive Data Register Full Flag — RDRF becomes set when a character transfers from the receive shifter into the receive
data register (SCID). To clear RDRF, read SCIS1 with RDRF = 1 and then read the SCI data register (SCID).
SCI Status Register 1 (SCIS1)
7
1
0
1
0
1
0
1
0
1
0
1
•
•
•
Normal SCI receiver operation.
SCI receiver in standby waiting for wake-up condition.
Normal transmitter operation.
Queue break character(s) to be sent.
Transmit data register (buffer) full.
Transmit data register (buffer) empty.
Transmitter active (sending data, a preamble, or a break).
Transmitter idle (transmission activity complete).
Receive data register empty.
Receive data register full.
Write to the SCI data register (SCID) to transmit new data
Queue a preamble by changing TE from 0 to 1
Queue a break character by writing 1 to SBK in SCIC2
TC
6
1
Table 141. SCIC2 Field Descriptions (continued)
Table 142. SCI Status Register 1 (SCIS1)
RDRF
Table 143. SCIS1 Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
Section 4.16.3.2.1, “Send Break and Queued
Operation” for more details.
IDLE
4
0
Description
Description
OR
3
0
Serial Communication Interface (S08SCIV4)
Idle” for more details.
NF
2
0
FE
1
0
Access: User read/write
pF
0
0
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