MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 204

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.3.2.6
Read: Anytime
Write: Never
Freescale Semiconductor
Address: 0x0026
Reset
POR
CNT[5:0]
Bit[15:0]
W
R
Field
Field
15–0
TBF
5–0
7
TBF
0
0
Trace Buffer Data Bits — The Trace Buffer Register is a window through which the 20-bit wide data lines of the Trace Buffer
may be read 16 bits at a time. Each valid read of DBGTB increments an internal trace buffer pointer which points to the next
address to be read. When the ARM bit is set the trace buffer is locked to prevent reading. The trace buffer can only be unlocked
for reading by writing to DBGTB with an aligned word write when the module is disarmed. The DBGTB register can be read
only as an aligned word, any byte reads or misaligned access of these registers return 0 and do not cause the trace buffer
pointer to increment to the next trace buffer address. Similarly reads while the debugger is armed or with the TSOURCE bit
clear, return 0 and do not affect the trace buffer pointer. The POR state is undefined. Other resets do not affect the trace buffer
contents.
Trace Buffer Full — The TBF bit indicates that the trace buffer has stored 64 or more lines of data since it was last armed. If
this bit is set, then all 64 lines will be valid data, regardless of the value of DBGCNT bits. The TBF bit is cleared when ARM in
DBGC1 is written to a one. The TBF is cleared by the power on reset initialization. Other system generated resets have no
affect on this bit
This bit is also visible at DBGSR[7]
Count Value — The CNT bits indicate the number of valid data 20-bit data lines stored in the Trace Buffer.
the correlation between the CNT bits and the number of valid data lines in the Trace Buffer. When the CNT rolls over to zero,
the TBF bit in DBGSR is set and incrementing of CNT will continue in end-trigger mode. The DBGCNT register is cleared when
ARM in DBGC1 is written to a one. The DBGCNT register is cleared by power-on-reset initialization but is not cleared by other
system resets. Thus should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the
number of valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when reading
from the trace buffer.
TBF
—
7
0
Debug Count Register (DBGCNT)
CNT[5:0]
000000
000001
000010
000100
000110
111111
—
6
0
0
…
= Unimplemented or Reserved
Table 284. Debug Count Register (DBGCNT)
Table 285. DBGCNT Field Descriptions
Table 283. DBGTB Field Descriptions
MM912_634 Advance Information, Rev. 4.0
—
5
0
Table 286. CNT Decoding Table
—
4
0
Description
Description
—
3
0
No data valid
63 lines valid
Description
2 lines valid
4 lines valid
6 lines valid
1 line valid
CNT
…
—
2
0
—
1
0
Table 286
—
0
0
shows
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