MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 222

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Field2 Bits in Normal and Loop1 Modes
4.32.4.5.4
Freescale Semiconductor
PC17
PC16
CSD
CVA
Bit
Pure PC Mode
3
2
1
0
Compressed
Mode
Source Destination Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a source
or destination address. This bit has no meaning in Compressed Pure PC mode.
Vector Indicator — In Normal and Loop1 mode this bit indicates if the corresponding stored address is a vector address.
Vector addresses are destination addresses, thus if CVA is set, then the corresponding CSD is also set. This bit has no
meaning in Compressed Pure PC mode.
Program Counter bit 17 — In Normal and Loop1 mode this bit corresponds to program counter bit 17.
Program Counter bit 16 — In Normal and Loop1 mode this bit corresponds to program counter bit 16.
Trace Buffer Organization (Compressed Pure PC mode)
Configured for end aligned triggering in compressed PurePC mode, then after rollover it is
possible that the oldest base address is overwritten. In this case all entries between the
pointer and the next base address have lost their base address following rollover. For
example in
new entry. Thus the entries on Lines 2 and 3 have lost their base address. For reconstruction
of program flow the first base address following the pointer must be used, in the example,
Line 4. The pointer points to the oldest entry, Line 2.
0
1
0
1
Number
Table 328. Trace Buffer Organization Example (Compressed PurePC mode)
Source Address
Destination Address
Non-Vector Destination Address
Vector Destination Address
Line 1
Line 2
Line 3
Line 4
Line 5
Line 6
Line
Table 329
Field 3
2-bits
00
01
00
10
00
11
if one line of rollover has occurred, Line 1, PC1, is overwritten with a
Bit 3
CSD
MM912_634 Advance Information, Rev. 4.0
Table 327. PCH Field Descriptions
Figure 68. Information Bits PCH
Field 2
6-bits
PC4
0
0
Bit 2
CVA
NOTE
Description
PC1 (Initial 18-bit PC Base Address)
PC6 (New 18-bit PC Base Address)
PC9 (New 18-bit PC Base Address)
PC17
Bit 1
Field 1
6-bits
PC3
PC8
0
PC16
Bit 0
Field 0
6-bits
PC2
PC5
PC7
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