MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 123

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note:
112.
A write to this register with the corresponding (FOC 3:0) data bit(s) set causes the action programmed for output compare on
channel “n” to occur immediately.The action taken is the same as if a successful comparison had just taken place with the TCn
register except the interrupt flag does not get set.
4.19.3.3.3
Setting the OC3Mn (n ranges from 0 to 2) will set the corresponding port to be an output port when the corresponding TIOSn (n
ranges from 0 to 2) bit is set to be an output compare.
4.19.3.3.4
Freescale Semiconductor
Offset
Note:
113.
Offset
Reset
Reset
W
R
OC3M[3-0]
FOC[3-0]
W
R
(112)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Field
Field
(113)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
3-0
3-0
0xC2
0xC3
7
0
0
Force Output Compare Action for Channel 3-0
Output Compare 3 Mask "n" Channel bit
A successful channel 3 output compare overrides any channel 2:0 compares. If forced
output compare on any channel occurs at the same time as the successful output compare
then forced output compare action will take precedence and interrupt flag will not get set.
Output Compare 3 Mask Register (OC3M)
A successful channel 3 output compare overrides any channel 2:0 compares. For each
OC3M bit that is set, the output compare action reflects the corresponding OC3D bit.
Output Compare 3 Data Register (OC3D)
7
0
0
0 - Force Output Compare Action disabled. Input Capture or Output Compare Channel Configuration
1 - Force Output Compare Action enabled
0 - Does not set the corresponding port to be an output port
1 - Sets the corresponding port to be an output port when this corresponding TIOS bit is set to be an output compare
6
0
0
6
0
0
Table 166. Output Compare 3 Mask Register (OC3M)
Table 168. Output Compare 3 Data Register (OC3D)
Table 165. CFORC - Register Field Descriptions
Table 167. OC3M - Register Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
0
NOTE
NOTE
4
0
0
4
0
0
Description
Description
OC3M3
OC3D3
3
0
3
0
Basic Timer Module - TIM (TIM16B4C)
OC3D2
OC3M2
2
0
2
0
OC3D1
OC3M1
1
0
Access: User read/write
1
0
Access: User read/write
OC3D0
OC3M0
0
0
0
0
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