MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 246

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.3.2.5
This register enables S12CPMU interrupt requests.
Read: Anytime
Write: Anytime
4.38.3.2.6
This register controls S12CPMU clock selection.
Read: Anytime
Write:
Freescale Semiconductor
0x0038
0x0039
Reset
Reset
LOCKIE
W
OSCIE
W
R
R
1.
2.
3.
4.
Field
RTIE
7
4
1
Only possible if PROT=0 (CPMUPROT register) in all MCU Modes (Normal and Special mode).
All bits in Special mode (if PROT=0).
PLLSEL, PSTP, PRE, PCE, RTIOSCSEL: In Normal mode (if PROT=0).
COPOSCSEL: In Normal mode (if PROT=0) until CPMUCOP write once is taken. If COPOSCSEL was cleared by
UPOSC=0 (entering full stop mode with COPOSCSEL=1 or insufficient OSCCLK quality), then COPOSCSEL can be
set again once.
PLLSEL
RTIE
Real Time Interrupt Enable Bit
PLL Lock Interrupt Enable Bit
Oscillator Corrupt Interrupt Enable Bit
7
0
7
1
S12CPMU Interrupt Enable Register (CPMUINT)
S12CPMU Clock Select Register (CPMUCLKS)
After writing CPMUCLKS register, it is strongly recommended to read back CPMUCLKS
register to make sure that write of PLLSEL, RTIOSCSEL and COPOSCSEL was successful.
0
1
0
1
0
1
Interrupt requests from RTI are disabled.
Interrupt will be requested whenever RTIF is set.
PLL LOCK interrupt requests are disabled.
Interrupt will be requested whenever LOCKIF is set.
Oscillator Corrupt interrupt requests are disabled.
Interrupt will be requested whenever OSCIF is set.
PSTP
6
0
0
6
0
Table 345. S12CPMU Interrupt Enable Register (CPMUINT)
= Unimplemented or Reserved
Table 347. S12CPMU Clock Select Register (CPMUCLKS)
= Unimplemented or Reserved
Table 346. CRGINT Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
0
LOCKIE
NOTE
4
0
4
0
0
Description
PRE
3
0
0
3
0
PCE
2
0
0
2
0
OSCSEL
OSCIE
RTI
1
0
1
0
OSCSEL
COP
0
0
0
0
0
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