MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 292

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.39.4.6
The SPI has one error condition:
4.39.4.6.1
If the SS input becomes low while the SPI is configured as a master, it indicates a system error where more than one master may
be trying to drive the MOSI and SCK lines simultaneously. This condition is not permitted in normal operation, the MODF bit in
the SPI status register is set automatically, provided the MODFEN bit is set.
In the special case where the SPI is in master mode and MODFEN bit is cleared, the SS pin is not used by the SPI. In this special
case, the mode fault error function is inhibited and MODF remains cleared. In case the SPI system is configured as a slave, the
SS pin is a dedicated input pin. Mode fault error doesn’t occur in slave mode.
If a mode fault error occurs, the SPI is switched to slave mode, with the exception that the slave output buffer is disabled. So
SCK, MISO, and MOSI pins are forced to be high impedance inputs to avoid any possibility of conflict with another output driver.
A transmission in progress is aborted and the SPI is forced into idle state.
If the mode fault error occurs in the bidirectional mode for a SPI system configured in master mode, output enable of the MOMI
(MOSI in bidirectional mode) is cleared if it was set. No mode fault error occurs in the bidirectional mode for SPI system
configured in slave mode.
The mode fault flag is cleared automatically by a read of the SPI status register (with MODF set) followed by a write to SPI control
register 1. If the mode fault flag is cleared, the SPI becomes a normal master or slave again.
4.39.4.7
4.39.4.7.1
In run mode with the SPI system enable (SPE) bit in the SPI control register clear, the SPI system is in a low-power, disabled
state. SPI registers remain accessible, but clocks to the core of this module are disabled.
4.39.4.7.2
Stop mode is dependent on the system. The SPI enters stop mode when the module clock is disabled (held high or low). If the
SPI is in master mode and exchanging data when the CPU enters stop mode, the transmission is frozen until the CPU exits stop
mode. After stop, data to and from the external SPI is exchanged correctly. In slave mode, the SPI will stay synchronized with
the master.
The stop mode is not dependent on the SPISWAI bit.
4.39.4.7.3
The reset values of registers and signals are described in
the registers and their bit fields.
4.39.4.7.4
The SPI only originates interrupt requests when SPI is enabled (SPE bit in SPICR1 set). The following is a description of how the
SPI makes a request and how the MCU should acknowledge that request. The interrupt vector offset and interrupt priority are
chip dependent.
The interrupt flags MODF, SPIF, and SPTEF are logically ORed to generate an interrupt request.
4.39.4.7.4.1
MODF occurs when the master detects an error on the SS pin. The master SPI must be configured for the MODF feature (see
Table
Freescale Semiconductor
•
•
390). After MODF is set, the current transfer is aborted and the following bit is changed:
Mode fault error
If a data transmission occurs in slave mode after reset without a write to SPIDR, it will transmit garbage, or the data last
received from the master before the reset.
Reading from the SPIDR after reset will always read zeros.
Error Conditions
Low Power Mode Options
Mode Fault Error
If a mode fault error occurs and a received data byte is pending in the receive shift register,
this data byte will be lost.
SPI in Run Mode
SPI in Stop Mode
Reset
Interrupts
MODF
MM912_634 Advance Information, Rev. 4.0
Section 4.39.3, “Memory Map and Register
NOTE
Definition”, which details
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