MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 244

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.3.2.3
The POSTDIV register controls the frequency ratio between the VCOCLK and the PLLCLK.
Read: Anytime
Write: Anytime if PLLSEL=1. Else write has no effect.
4.38.3.2.4
This register provides S12CPMU status bits and flags.
Read: Anytime
Write: Refer to each bit for individual write conditions
Freescale Semiconductor
Note:
182.
183.
184.
0x0036
0x0037
Reset
Reset
W
W
R
R
If PLL is selected (PLLSEL=1)
If PLL is locked (LOCK=1)
If PLL is not locked (LOCK=0)
PORF is set to 1 when a power on reset occurs. Unaffected by System Reset.
LVRF is set to 1 when a low voltage reset occurs. Unaffected by System Reset. Set by power on reset.
ILAF is set to 1 when an illegal address reset occurs. Unaffected by System Reset. Cleared by power on reset.
RTIF
7
0
0
7
0
S12CPMU Post Divider Register (CPMUPOSTDIV)
S12CPMU Flags Register (CPMUFLG)
Table 341. Reference Clock Frequency Selection if OSC_LCP is enabled
PORF
(182)
Table 342. S12CPMU Post Divider Register (CPMUPOSTDIV)
6
0
0
6
= Unimplemented or Reserved
= Unimplemented or Reserved
REFCLK Frequency Ranges (OSCE=1)
Table 343. S12CPMU Flags Register (CPMUFLG)
1.0 MHz <= f
6.0 MHz < f
2.0 MHz < f
f bus
f PLL
f PLL
LVRF
MM912_634 Advance Information, Rev. 4.0
(183)
5
0
0
5
=
f
REF
=
=
f PLL
------------
--------------------------------------- -

REF
f VCO
------------- -
REF
>12MHz
POSTDIV
2
REF
4
<= 12.0 MHz
<= 6.0 MHz
<= 2.0 MHz
f VCO
LOCKIF
4
0
4
0
+
1

LOCK
3
0
3
0
REFFRQ[1:0]
00
01
10
11
POSTDIV[4:0]
ILAF
(184)
2
0
2
OSCIF
1
1
1
0
UPOSC
0
1
0
0
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