MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 240

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38.2.4
4.38.2.5
Pins V
Internal precision reference circuits are supplied from these signals.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between V
4.38.2.6
This supply domain is monitored by the Low Voltage Reset circuit.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between VDDX and VSSX can improve the quality of this supply.
4.38.2.7
Node VDD is a device internal supply output of the voltage regulator that provides the power supply for the core logic. This supply
domain is monitored by the Low Voltage Reset circuit.
4.38.2.8
Node VDDF is a device internal supply output of the voltage regulator that provides the power supply for the NVM logic. This
supply domain is monitored by the Low Voltage Reset circuit
4.38.2.9
This pin provides the signal selected via APIES and is enabled with APIEA bit. See device specification to which pin it connects.
4.38.2.10
These pins allow to measure internal VDDF, VDD, VDDPLL.
4.38.2.11
This signal is connected to a device pin and allows measuring internal clocks if cpmu_test_clk_en bit is set.
4.38.2.12
This signal is connected to a device pin and allows measuring the internal PLL filter node if cpmu_test_xfc_en bit is set.
4.38.2.13
With the ipt_trim_ld_en signal of the PTI, the trim values for VDD and VDDF of the VREG are loaded into CPMUTEST3 register
which directly trims the VREG.
4.38.3
This section provides a detailed description of all registers accessible in the S12CPMU.
4.38.3.1
The S12CPMU registers are shown in
Freescale Semiconductor
DDA
and V
Memory Map and Registers
VSS — Ground Pin
VSS must be grounded.
VDDX, VSSX— Pad Supply Pins
VDD — Internal Regulator Output Supply (Core Logic)
VDDF — Internal Regulator Output Supply (NVM Logic)
API_EXTCLK
vddf_test, vdd_test, vddpll_test — supply testmode pins
cpmu_test_clk
cpmu_test_xfc
REGFT[2:0] and REGT[2:0]
Module Memory Map
SSA
Depending on the device package following device supply pins are maybe combined into
one supply pin: VDDR, VDDX and VDDA.
Depending on the device package following device supply pins are maybe combined into
one supply pin: VSS, VSSX and VSSA.
Please refer to the device Reference Manual for information if device supply pins are
combined into one supply pin for certain packages and which supply pins are combined
together.
An off-chip decoupling capacitor (100 nF...220 nF, X7R ceramic) between the combined
supply pin pair can improve the quality of this supply.
are used to supply the analog parts of the regulator.
— API external clock output pin
Figure
VDDA, VSSA — Regulator Reference Supply Pins
MM912_634 Advance Information, Rev. 4.0
337.
NOTE
DDA
and V
SSA
can improve the quality of this supply.
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