MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 236

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.38
4.38.1
This specification describes the function of the Clock, Reset and Power Management Unit.
4.38.1.1
The Pierce Oscillator (OSCLCP) contains circuitry to dynamically control current gain in the output amplitude. This ensures a
signal with low harmonic distortion, low power and good noise immunity.
The Voltage Regulator (IVREG) has the following features:
The Phase Locked Loop (PLL) has the following features:
The Internal Reference Clock (IRC1M) has the following features:
Other features of the S12CPMU include
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The Pierce oscillator (OSCLCP) provides a robust, low-noise and low-power external clock source. It is designed for
optimal start-up margin with typical crystal oscillators.
The Voltage regulator (IVREG) operates from the range 3.13 to 5.5 V. It provides all the required chip internal voltages
and voltage monitors.
The Phase Locked Loop (PLL) provides a highly accurate frequency multiplier with internal filter.
The Internal Reference Clock (IRC1M) provides a 1.0 MHz clock.
Supports crystals or resonators from 4.0 to 16 MHz.
High noise immunity due to input hysteresis and spike filtering.
Low RF emissions with peak-to-peak swing limited dynamically
Transconductance (gm) sized for optimum start-up margin for typical crystals
Dynamic gain control eliminates the need for external current limiting resistor
Integrated resistor eliminates the need for external bias resistor.
Low power consumption: Operates from internal 1.8 V (nominal) supply, Amplitude control limits power
Input voltage range from 3.13 to 5.5 V
Low-voltage detect (LVD) with low-voltage interrupt (LVI)
Power-on reset (POR)
Low-voltage reset (LVR)
during scan pattern execution option to go to RPM to support IDDq test.
external voltage reference used for HV-stress test and MIM screen, the external voltage on VDDA, divided by series
resistors, will be used as input to the regulating loop of the IVREG
highly accurate and phase locked frequency multiplier
Configurable internal filter for best stability and lock time.
Frequency modulation for defined jitter and reduced emission
Automatic frequency lock detector
Interrupt request on entry or exit from locked condition
Reference clock either external (crystal) or internal square wave (1.0 MHz IRC1M) based.
PLL stability is sufficient for LIN communication, even if using IRC1M as reference clock
Trimmable in frequency
Factory trimmed value for 1.0 MHz in Flash Memory, can be overwritten by application if required
Clock monitor to detect loss of crystal
Autonomous periodical interrupt (API)
Bus Clock Generator
— Clock switch to select either PLLCLK or external crystal/resonator based Bus Clock
— PLLCLK divider to adjust system speed
System Reset generation from the following possible sources:
— Power-on reset (POR)
— Low-voltage reset (LVR)
— Illegal address access
— COP timeout
— Loss of oscillation (clock monitor fail)
— External pin RESET
S12 Clock, Reset and Power Management Unit (S12CPMU)
Introduction
Features
MM912_634 Advance Information, Rev. 4.0
236