MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 168

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.29.3.2.2
Read: Anytime
Write: anytime in special SS, write-one in NS.
This register determines the position of the 256 Byte direct page within the memory map.It is valid for both global and local
mapping scheme.
Freescale Semiconductor
Address: 0x0011
Reset
DP[15:8]
W
MODC
R
Field
Field
7–0
7
DP15
Mode Select Bit — This bit controls the current operating mode during RESET high (inactive). The external mode pin MODC
determines the operating mode during RESET low (active). The state of the pin is registered into the respective register bit
after the RESET signal goes inactive (see
Write restrictions exist to disallow transitions between certain modes.
Attempting non authorized transitions will not change the MODE bit, but it will block further writes to the register bit except in
special modes.
Write accesses to the MODE register are blocked when the device is secured.
Direct Page Index Bits 15–8 — These bits are used by the CPU when performing accesses using the direct addressing mode.
These register bits form bits [15:8] of the local address (see
7
0
Direct Page Register (DIRECT)
DP14
Figure 48. Mode Transition Diagram When MCU is Unsecured
Bit15
6
0
Single-Chip
Normal
(NS)
1
Table 249. DIRECT Field Descriptions
Figure 49. DIRECT Address Mapping
DP [15:8]
Table 247. MODE Field Descriptions
DP13
Table 248. Direct Register (DIRECT)
MM912_634 Advance Information, Rev. 4.0
5
0
1
Figure
CPU Address [15:0]
RESET
DP12
48).
4
0
Bit8
1
Description
Description
Bit7
Figure
0
DP11
3
0
49).
Figure 48
Single-Chip
Special
(SS)
illustrates all allowed mode changes.
0
DP10
2
0
Bit0
DP9
1
0
DP8
0
0
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