MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 214

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.4
This section provides a complete functional description of the DBG module. If the part is in secure mode, the DBG module can
generate breakpoints but tracing is not possible.
4.32.4.1
Arming the DBG module by setting ARM in DBGC1 allows triggering the state sequencer, storing of data in the trace buffer and
generation of breakpoints to the CPU. The DBG module is made up of four main blocks, the comparators, control logic, the state
sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU. All comparators can be configured to monitor address bus activity.
Comparator A can also be configured to monitor data bus activity and mask out individual data bus bits during a compare.
Comparators can be configured to use R/W and word/byte access qualification in the comparison. A match with a comparator
register value can initiate a state sequencer transition to another state (see
possible. Using a forced match, a state sequencer transition can occur immediately on a successful match of system busses and
comparator registers. Whilst tagging, at a comparator match, the instruction opcode is tagged and only if the instruction reaches
the execution stage of the instruction queue can a state sequencer transition occur. In the case of a transition to Final State, bus
tracing is triggered and/or a breakpoint can be generated.
A state sequencer transition to final state (with associated breakpoint, if enabled) can be initiated by writing to the TRIG bit in the
DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and must be read out using standard 16-bit word
reads.
4.32.4.2
The DBG contains three comparators, A, B and C. Each comparator compares the system address bus with the address stored
in DBGXAH, DBGXAM, and DBGXAL. Furthermore, comparator A also compares the data buses to the data stored in DBGADH,
DBGADL and allows masking of individual data bus bits.
All comparators are disabled in BDM and during BDM accesses.
The comparator match control logic (see
address range, whereby either an access inside or outside the specified range generates a match condition. The comparator
configuration is controlled by the control register contents and the range control by the DBGC2 contents.
Freescale Semiconductor
TAGHITS
SECURE
CPU BUS
READ TRACE DATA (DBG READ DATA BUS)
Functional Description
S12SDBG Operation
Comparator Modes
COMPARATOR A
COMPARATOR C
COMPARATOR B
Figure
MM912_634 Advance Information, Rev. 4.0
66) configures comparators to monitor the buses for an exact address or an
Figure 66. DBG Overview
MATCH1
MATCH0
MATCH2
Figure
CONTROL
MATCH
LOGIC
TAG &
67). Either forced or tagged matches are
TRANSITION
STATE
BREAKPOINT REQUESTS
TO CPU
TRACE BUFFER
TAGS
STATE SEQUENCER
STATE
TRACE
CONTROL
TRIGGER
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