MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 72

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.9.1.3
Configuring the Forced Wake-up Multiplier (FWM) in the Timing Control Register (TCR) will enable the forced wake-up based on
the selected Cyclic Sense Timing (CST). Forced Wake-up can be combined with all other wake-up sources considering the timing
dependencies.
4.9.1.4
While in Low-Power mode the MM912_634 analog die monitors the activity on the LIN bus. A dominant pulse longer than
t
short-to-ground bus condition.
4.9.1.5
Receiving a Normal mode request via the D2D interface (MODE=0, Mode Control Register (MCR)) will result in a wake-up from
stop mode. As this condition is controlled by the MCU, no wake-up status bit does indicate this wake-up source.
4.9.1.6
While in Stop mode, a Reset due to a VDD low voltage condition or an external Reset applied on the RESET_A pin will result in
a Wake-up with immediate transition to Reset mode. In this case, the LVR or EXR bits in the Reset Status Register will indicate
the source of the event.
4.9.1.7
While in Sleep mode, a supply voltage VS1 < VPOR will result in a transition to Power On mode.
4.9.2
4.9.2.1
Note:
Freescale Semiconductor
PROPWL
Offset
69.
Reset
W
5 - L5WE
4 - L4WE
R
CSSEL
Field
(69)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
7-6
followed by a dominant to recessive transition will cause a LIN Wake-up. This behavior protects the system from a
0x12
Register Definition
Forced Wake-up
LIN - Wake-up
D2D - Wake-up (Stop Mode only)
Wake-up Due to Internal / External Reset (STOP Mode Only)
Wake-up Due to Loss of Supply Voltage (SLEEP Mode Only)
Wake-up Control Register (WCR)
Cyclic Sense Select - Configures the HSx output for the cyclic sense event. Note, with no LxWE selected - only the selected
HSx output will be switched periodically, no Lx state change would be detected. For all configurations, the Forced Wake-up
can be activated in parallel in
Wake-up Input 5 Enabled - L5 Wake-up Select Bit.
Wake-up Input 4 Enabled - L4 Wake-up Select Bit.
7
0
00 - Cyclic Sense Off
01 - Cyclic Sense with periodic HS1on
10 - Cyclic Sense with periodic HS2 on
11 - Cyclic Sense with periodic HS1 and HS2 on.
0 - L5 Wake-up Disabled
1 - L5 Wake-up Enabled
0 - L4 Wake-up Disabled
1 - L4 Wake-up Enabled
CSSEL
6
0
Table 95. WCR - Register Field Descriptions
Table 94. Wake-up Control Register (WCR)
Section 4.9.2.2, “Timing Control Register (TCR)
L5WE
MM912_634 Advance Information, Rev. 4.0
5
1
L4WE
4
1
Description
L3WE
3
1
L2WE
2
1
Wake-up / Cyclic Sense
L1WE
1
1
Access: User read/write
L0WE
0
1
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