MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 308

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

All bits in the FRSV3 register read 0 and are not writable.
4.40.3.2.15
This Flash register is reserved for factory testing.
All bits in the FRSV4 register read 0 and are not writable.
4.40.3.2.16
The FOPT register is the Flash option register.
All bits in the FOPT register are readable but are not writable.
During the reset sequence, the FOPT register is loaded from the Flash nonvolatile byte in the Flash configuration field at global
address 0x3_FF0E located in P-Flash memory (see
fault is detected while reading the P-Flash phrase containing the Flash nonvolatile byte during the reset sequence, all bits in the
FOPT register will be set.
4.40.3.2.17
This Flash register is reserved for factory testing.
Freescale Semiconductor
Reset
Reset
Reset
NV[7:0]
W
W
W
W
R
R
R
R
Field
7–0
Nonvolatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the device user guide for proper use of the NV
bits.
7
0
0
7
0
0
7
F
7
0
Flash Reserved4 Register (FRSV4)
Flash Option Register (FOPT)
Flash Reserved5 Register (FRSV5)
F
6
0
0
6
0
0
6
6
0
= Unimplemented or Reserved
= Unimplemented or Reserved
= Unimplemented or Reserved
Table 436. Flash Reserved3 Register (FRSV3)
Table 437. Flash Reserved4 Register (FRSV4)
Table 440. Flash Reserved5 Register (FRSV5)
Table 438. Flash Option Register (FOPT)
Table 439. FOPT Field Descriptions
MM912_634 Advance Information, Rev. 4.0
F
5
0
0
5
0
0
5
5
0
Table
404) as indicated by reset condition F in
4
0
0
4
0
0
4
F
4
0
Description
NV[7:0]
3
0
0
3
0
0
3
F
3
0
2
0
0
2
0
0
2
F
2
0
Figure
F
1
0
0
1
0
0
1
1
0
438. If a double bit
0
0
0
0
0
0
0
F
0
0
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