MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 270

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.
4.38.4.6.3
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is based on the external
oscillator. The adaptive spike filter and detection logic can be enabled which uses the VCOCLK to filter and qualify the external
oscillator clock.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
Since the Adaptive Oscillator Filter (adaptive spike filter and detection logic) uses the VCOCLK to continuously filter and qualify
the external oscillator clock, loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well
(UPOSC=0).
The impact of loosing the oscillator status in PBE mode is as follows:
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any time.
In the PBE mode, not every noise disturbance can be indicated by bits LOCK and UPOSC (both bits are based on the Bus Clock
domain). There are clock disturbances possible, after which UPOSC and LOCK both stay asserted while occasional pauses on
the filtered OSCCLK and resulting Bus Clock occur. The adaptive spike filter is still functional and protects the Bus Clock from
frequency overshoot due to spikes on the external oscillator clock. The filtered OSCCLK and resulting Bus Clock will pause until
the PLL has stabilized again.
4.38.5
4.38.5.1
All reset sources are listed in
4.38.5.2
Upon detection of any reset of
cycles the RESET pin is released. The reset generator of the S12CPMU waits for additional 256 PLLCLK cycles and then
samples the RESET pin to determine the originating source.
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Make sure the PLL configuration is valid.
Optionally the adaptive spike filter and detection logic can be enabled by calculating the integer value for the
OSCFIL[4:0] bits and setting the bandwidth (OSCBW) accordingly.
Enable the external Oscillator (OSCE bit)
Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up and additionally being qualified if the Adaptive
Oscillator Filter is enabled (UPOSC=1).
Clear all flags in the CPMUFLG register to be able to detect any status bit change.
Optionally status interrupts can be enabled (CPMUINT register).
Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the PLL locks again.
Resets
General
Description of Reset Operation
PLL Bypassed External Mode (PBE)
Low Voltage Reset (LVR)
Power-On Reset (POR)
Illegal Address Reset
Clock Monitor Reset
Table
External pin RESET
Table
Reset Source
COP Reset
384. Refer to MCU specification for related vector addresses and priorities
384, an internal circuit drives the RESET pin low for 512 PLLCLK cycles. After 512 PLLCLK
MM912_634 Advance Information, Rev. 4.0
Table 384. Reset Summary
Table 385
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
shows which vector will be fetched.
Local Enable
None
None
None
None
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