MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 269

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The use of the filter function is only possible if the VCOCLK-to-OSCCLK ratio divided by two ((f
This integer value must be written to the OSCFILT[4:0] bits.
If enabled, the Adaptive Oscillator Filter is sampling the incoming external oscillator clock signal (EXTAL) with the VCOCLK
frequency.
Using VCOCLK, a time window is defined during which an edge of the OSCCLK is expected. In case of OSCBW = 1 the width
of this window is three VCOCLK cycles, if the OSCBW = 0 it is one VCOCLK cycle.
The noise detection is active for certain combinations of OSCFILT[4:0] and OSCBW bit settings as shown in
4.38.4.6
4.38.4.6.1
This mode is the default mode after System Reset or Power-on Reset.
The Bus Clock is based on the PLLCLK, the reference clock for the PLL is internally generated (IRC1M). The PLL is configured
to 64 MHz VCOCLK with POSTDIV set to 0x03. If locked (LOCK=1) this results in a PLLCLK of 16 MHz and a Bus Clock of
8.0 MHz. The PLL can be re-configured to other bus frequencies.
The clock sources for COP and RTI are based on the internal reference clock generator (IRC1M).
4.38.4.6.2
In this mode, the Bus Clock is based on the PLLCLK as well (like PEI). The reference clock for the PLL is based on the external
oscillator. The adaptive spike filter and detection logic which uses the VCOCLK to filter and qualify the external oscillator clock
can be enabled.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
Since the Adaptive Oscillator Filter (adaptive spike filter and detection logic) uses the VCOCLK to continuously filter and qualify
the external oscillator clock, loosing PLL lock status (LOCK=0) means loosing the oscillator status information as well
(UPOSC=0).
The impact of loosing the oscillator status in PEE mode is as follows:
Freescale Semiconductor
1.
2.
3.
4.
5.
6.
Configure the PLL for desired bus frequency.
Optionally the adaptive spike filter and detection logic can be enabled by calculating the integer value for the
OSCFIL[4:0] bits and setting the bandwidth (OSCBW) accordingly.
Enable the external Oscillator (OSCE bit).
Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up and additionally being qualified if the Adaptive
Oscillator Filter is enabled (UPOSC =1).
Clear all flags in the CPMUFLG register to be able to detect any future status bit change.
Optionally status interrupts can be enabled (CPMUINT register).
System Clock Configurations
If the LOCK bit is clear due to severe noise disturbance on the external oscillator clock the
PLLCLK is derived from the VCO clock (with its actual frequency) divided by four (see
alsoSection 4.38.3.2.3, “S12CPMU Post Divider Register
If the VCOCLK frequency is higher than 25 MHz the wide bandwidth must be selected
(OSCBW = 1).
PLL Engaged Internal Mode (PEI)
PLL Engaged External Mode (PEE)
OSCFILT[4:0]
2 or 3
>=4
0
1
Table 383. Noise Detection Settings
MM912_634 Advance Information, Rev. 4.0
OSCBW
x
x
0
1
x
NOTE
NOTE
Detection
disabled
disabled
disabled
active
active
(CPMUPOSTDIV)).
VCO
disabled
active
active
active
active
Filter
/ f
OSC
)/2) is an integer number.
Table
383.
269