MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 137

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.20.4.2.2
4.20.4.2.3
Freescale Semiconductor
Note:
Offset
129.
Note:
130.
Offset
Reset
Reset
6 - 2p5CLF
CCNT3…0
W
R
W
R
7 - SCF
(129)
Field
(130)
Field
15-0
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
CHx
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
3-0
0x81
0x82 (0x82 and 0x83 for 8-Bit access)
CH15
15
0
SCF
7
0
Sequence Complete Flag. Reading the ADC Status Register (ASR) will clear the Flag.
ADC Reference Voltage Current Limitation Flag
Conversion Counter Status. The content of CCNT reflects the current channel in conversion and the conversion of CCNT-1
being complete. The conversion order is CH15, CH0, CH1,..., CH14.
Channel Select - If 1, the selected channel is included into the sequence. Writing ACCR will stop the current sequence and
restart. Writing ACCR=0 will stop the conversion, All CCx flags will be cleared when ACCR is written.Conversion will start
after write. 16-Bit write operation recommended, writing 8-bit: Only writing the High Byte will start the conversion with
Channel 15, if selected. Write to the Low Byte will not start a conversion.
Measure individual Channels by writing a sequence of one channel. Channel 15 needs to be selected in order to have the
offset compensation functional.
ADCRST is strongly recommended to be set during D2D clock frequency changes.
ADC Status Register (ASR)
ADC Conversion Control Register (ACCR)
CH14
14
0
13
0
0
2p5CLF
6
0
CH12
12
Table 203. ADC Conversion Control Register (ACCR)
0
Table 204. ACCR - Register Field Descriptions
Table 202. ACR - Register Field Descriptions
CH11
11
0
Table 201. ADC Status Register (ASR)
MM912_634 Advance Information, Rev. 4.0
5
0
0
CH10
10
0
CH9
9
0
NOTE
0
4
0
CH8
8
0
Description
Description
CH7
7
0
CCNT3
3
1
CH6
6
0
CH5
5
0
CCNT2
2
1
CH4
4
0
CH3
3
0
CCNT1
1
1
Access: User read/write
Access: User read/write
CH2
2
0
CH1
1
0
CCNT0
0
1
CH0
0
0
137