MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 95

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.14.4.2.1
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx bits are set (PWMEx = 1),
the associated PWM output signal is enabled immediately. However, the actual PWM waveform is not available on the associated
PWM output until its clock source begins its next cycle due to the synchronization of PWMEx and the clock source.
On the front end of the PWM timer, the clock is enabled to the PWM circuit by the PWMEx bit being high. There is an
edge-synchronizing circuit to guarantee that the clock will only be enabled or disabled at an edge. When the channel is disabled
(PWMEx = 0), the counter for the channel does not count.
4.14.4.2.2
Each channel has a polarity bit to allow starting a waveform cycle with a high or low signal. This is shown on the block diagram
as a mux select of either the Q output or the Q output of the PWM output flip flop. When one of the bits in the PWMPOL register
is set, the associated PWM channel output is high at the beginning of the waveform, then goes low when the duty count is
reached. Conversely, if the polarity bit is zero, the output starts low and then goes high when the duty count is reached.
4.14.4.2.3
Dedicated period and duty registers exist for each channel and are double buffered, so if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
Freescale Semiconductor
D2D Clock
•
•
•
PWMEx
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
(Clock Edge
Sync)
Gate
PWM Enable
The first PWM cycle after enabling the channel can be irregular.
PWM Polarity
PWM Period and Duty
Up/Down
8-Bit Counter
PWMCNTx
Q
Q
Figure 24. PWM Timer Channel Block Diagram
Reset
T
R
MM912_634 Advance Information, Rev. 4.0
NOTE
8-bit Compare =
8-bit Compare =
PWMPERx
PWMDTYx
CAEx
T
R
PWM Control Module (PWM8B2C)
Q
Q
PPOLx
M
U
X
PWM
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