MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 290

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The SS line can remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred
in systems having a single fixed master and a single slave that drive the MISO data line.
The SPI interrupt request flag (SPIF) is common to both the master and slave modes. SPIF gets set one half SCK cycle after the
last SCK edge.
4.39.4.4
Baud rate generation consists of a series of divider stages. Six bits in the SPI baud rate register (SPPR2, SPPR1, SPPR0, SPR2,
SPR1, and SPR0) determine the divisor to the SPI module clock which results in the SPI baud rate.
The SPI clock rate is determined by the product of the value in the baud rate preselection bits (SPPR2–SPPR0) and the value
in the baud rate selection bits (SPR2–SPR0). The module clock divisor equation is shown in
When all bits are clear (the default condition), the SPI module clock is divided by 2. When the selection bits (SPR2–SPR0) are
001 and the preselection bits (SPPR2–SPPR0) are 000, the module clock divisor becomes 4. When the selection bits are 010,
the module clock divisor becomes 8, etc.
When the preselection bits are 001, the divisor determined by the selection bits is multiplied by 2. When the preselection bits are
010, the divisor is multiplied by 3, etc. See
clock. The two sets of selects allows the clock to be divided by a non-power of two to achieve other baud rates such as divide by
6, divide by 10, etc.
Freescale Semiconductor
End of Idle State
SCK Edge Number
SCK (CPOL = 0)
SCK (CPOL = 1)
SAMPLE I
MOSI/MISO
CHANGE O
CHANGE O
SEL SS (O)
Master only
SEL SS (I)
t
t
t
MOSI pin
MISO pin
L
T
I
Back-to-back transfers in master mode
In master mode, if a transmission has completed and new data is available in the SPI data register, this data is sent out
immediately without a trailing and minimum idle time.
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
= Minimum idling time between transfers (minimum SS high time), not required for back-to-back transfers
= Minimum leading time before the first SCK edge, not required for back-to-back transfers
= Minimum trailing time after the last SCK edge
Figure 111. SPI Clock Format 1 (CPHA = 1), with 16-Bit Transfer Width Selected (XFRW = 1)
SPI Baud Rate Generation
t
L
1
MSB
LSB
2
3
Bit 14
Bit 1
BaudRateDivisor = (SPPR + 1)  2
4
5
Bit 13
Begin
Bit 2
6
Table 396
7
Bit 12
MM912_634 Advance Information, Rev. 4.0
Bit 3
8
9
Bit 11
Bit 4
10
11
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
for baud rate calculations for all bit conditions, based on a 25 MHz bus
Bit 5
12
13
Bit 6
14
Transfer
15
Bit 7 Bit 8 Bit 9 Bit 10 Bit 11Bit 12Bit 13Bit 14
16
17
18
19
(SPR + 1)
20
21
Bit 5
22
23
Bit 4 Bit 3 Bit 2 Bit 1
24
25
End
26
27
28
Equation
29
30
31
MSB
LSB
32
t
112.
T
Begin of Idle State
t
I
Minimum 1/2 SCK
for t
t
L
T
, t
l
, t
L
Eqn. 112
290