MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 205

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.32.3.2.7
There is a dedicated control register for each of the state sequencer states 1 to 3 that determines if transitions from that state are
allowed, depending upon comparator matches or tag hits, and defines the next state for the state sequencer following a match.
The three debug state control registers are located at the same address in the register address map (0x0027). Each register can
be accessed using the COMRV bits in DBGC1 to blend in the required register. The COMRV = 11 value blends in the match flag
register (DBGMFR).
4.32.3.2.7.1
Read: If COMRV[1:0] = 00
Write: If COMRV[1:0] = 00 and DBG is not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the targeted next state whilst in
State1. The matches refer to the match channels of the comparator match control logic as depicted in
in 4.32.3.2.8.1. Comparators must be enabled by setting the comparator enable bit in the associated DBGXCTL control register.
Freescale Semiconductor
Address: 0x0027
Reset
SC[3:0]
0000
0001
0010
SC[3:0]
W
R
Field
3–0
TBF
1
1
These bits select the targeted next state whilst in State1, based upon the match event.
7
0
0
Debug State Control Registers
Debug State Control Register 1 (DBGSCR1)
CNT[5:0]
000000
000001
111110
6
0
0
…
…
= Unimplemented or Reserved
Table 288. Debug State Control Register 1 (DBGSCR1)
Table 287. State Control Register Access Encoding
COMRV
Table 290. State1 Sequencer Next State Selection
00
01
10
11
Table 289. DBGSCR1 Field Descriptions
MM912_634 Advance Information, Rev. 4.0
Description (Unspecified matches have no effect)
5
0
0
Table 286. CNT Decoding Table
Any match to Final State
Visible State Control Register
4
0
0
ARM bit will be cleared and the tracing session ends.
oldest data has been overwritten by most recent data
Match2 to State2
Match1 to State3
64 lines valid; if using Begin trigger alignment,
Description
DBGSCR1
DBGSCR2
DBGSCR3
DBGMFR
SC3
3
0
64 lines valid,
Description
SC2
2
0
Figure 65
SC1
1
0
and described
SC0
0
0
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