MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 90

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.14.3.5
Each channel has a dedicated 8-bit up/down counter, which runs at the rate of the selected clock source. The counter can be
read at any time without affecting the count or the operation of the PWM channel. In left aligned output mode, the counter counts
from 0 to the value in the period register - 1. In center aligned output mode, the counter counts from 0 up to the value in the period
register and then back down to 0.
Any value written to the counter causes the counter to reset to $00, the counter direction to be set to up, the immediate load of
both duty and period registers with values from the buffers, and the output to change according to the polarity bit. The counter is
also cleared at the end of the effective period (see
Aligned Outputs”
channel becomes enabled (PWMEx = 1), the associated PWM counter starts at the count in the PWMCNTx register. For more
detailed information on the operation of the counters, see
Note:
4.14.3.6
There is a dedicated period register for each channel. The value in this register determines the period of the associated PWM
channel.
The period registers for each channel are double buffered, so if they change while the channel is enabled, the change will NOT
take effect until one of the following occurs:
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some variation in between.
If the channel is not enabled, then writes to the period register will go directly to the latches as well as the buffer.
See
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA, or SB) and multiply it
by the value in the period register for that channel:
Freescale Semiconductor
Note:
Offset
Offset
86.
85.
Reset
Reset
W
R
W
R
•
•
•
Section 4.14.4.2.3, “PWM Period and Duty”
(86)
(85)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
The effective period ends
The counter is written (counter resets to $00)
The channel is disabled
0x64/0x65
0x63
Bit 7
Bit 7
PWM Channel Counter Registers (PWMCNTx)
PWM Channel Period Registers (PWMPERx)
7
0
0
7
0
for more details). When the channel is disabled (PWMEx = 0), the PWMCNTx register does not count. When a
Writing to the counter while the channel is enabled can cause an irregular PWM cycle to
occur.
Reads of this register return the most recent value written. Reads do not necessarily return
the value of the currently active period due to the double buffering scheme.
6
0
0
6
0
6
6
Table 127. PWM Channel Counter Registers (PWMCNTx)
Table 126. PWM Scale B Register (PWMSCLB)
MM912_634 Advance Information, Rev. 4.0
5
0
0
5
0
5
5
for more information.
Section 4.14.4.2.5, “Left Aligned Outputs”
Section 4.14.4.2.4, “PWM Timer
NOTE
NOTE
4
0
4
0
0
4
4
3
0
3
0
0
3
3
2
0
2
2
0
0
Counters”.
2
PWM Control Module (PWM8B2C)
and
Section 4.14.4.2.6, “Center
1
0
1
1
0
0
Access: User read/write
1
Access: User read/write
Bit 0
Bit 0
0
0
0
0
0
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