MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 277

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.39.3.2.1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Reset
W
R
LSBFE
SPTIE
MSTR
CPHA
SSOE
CPOL
Field
SPIE
SPE
7
6
5
4
3
2
1
0
SPIE
SPI Interrupt Enable Bit — This bit enables SPI interrupt requests, if SPIF or MODF status flag is set.
SPI System Enable Bit — This bit enables the SPI system and dedicates the SPI port pins to SPI system functions. If SPE
is cleared, SPI is disabled and forced into idle state, status bits in SPISR register are reset.
SPI Transmit Interrupt Enable — This bit enables SPI interrupt requests, if SPTEF flag is set.
SPI Master/Slave Mode Select Bit — This bit selects whether the SPI operates in master or slave mode. Switching the SPI
from master to slave or vice versa forces the SPI system into idle state.
SPI Clock Polarity Bit — This bit selects an inverted or non-inverted SPI clock. To transmit data between SPI modules, the
SPI modules must have identical CPOL values. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
SPI Clock Phase Bit — This bit is used to select the SPI clock format. In master mode, a change of this bit will abort a
transmission in progress and force the SPI system into idle state.
Slave Select Output Enable — The SS output feature is enabled only in master mode, if MODFEN is set, by asserting the
SSOE as shown in
system into idle state.
LSB-First Enable — This bit does not affect the position of the MSB and LSB in the data register. Reads and writes of the
data register always have the MSB in the highest bit position. In master mode, a change of this bit will abort a transmission in
progress and force the SPI system into idle state.
7
0
SPI Control Register 1 (SPICR1)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
SPI interrupts disabled.
SPI interrupts enabled.
SPI disabled (lower power consumption).
SPI enabled, port pins are dedicated to SPI functions.
SPTEF interrupt disabled.
SPTEF interrupt enabled.
SPI is in slave mode.
SPI is in master mode.
Active-high clocks selected. In idle state SCK is low.
Active-low clocks selected. In idle state SCK is high.
Sampling of data occurs at odd edges (1,3,5,...) of the SCK clock.
Sampling of data occurs at even edges (2,4,6,...) of the SCK clock.
Data is transferred most significant bit first.
Data is transferred least significant bit first.
SPE
6
0
Table
390. In master mode, a change of this bit will abort a transmission in progress and force the SPI
Table 388. SPI Control Register 1 (SPICR1)
Table 389. SPICR1 Field Descriptions
SPTIE
MM912_634 Advance Information, Rev. 4.0
5
0
MSTR
4
0
Description
CPOL
3
0
CPHA
2
1
SSOE
1
0
LSBFE
0
0
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