MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 178

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.30.2
The INT module has no external signals.
4.30.3
This section provides a detailed description of all registers accessible in the INT module.
4.30.3.1
This section describes in address order all the INT registers and their individual bits.
4.30.3.1.1
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: 0x001F
IVB_ADDR[7:0]
Reset
W
R
Field
7–0
Peripheral
Interrupt Requests
External Signal Description
Memory Map and Register Definition
Register Descriptions
7
1
Interrupt Vector Base Register (IVBR)
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of reset these bits
are set to 0xFF (i.e., vectors are located at 0xFF80–0xFFFE) to ensure compatibility to HCS12.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine the reset
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of IVBR are
vector address. Therefore, changing the IVBR has no effect on the location of the three reset vectors
(0xFFFA–0xFFFE).
ignored and the upper byte of the vector address is fixed as “0xFF”. This is done to enable handling of all
non-maskable interrupts in the BDM firmware.
6
1
Non I bit Maskable Channels
I bit Maskable Channels
Table 256. Interrupt Vector Base Register (IVBR)
MM912_634 Advance Information, Rev. 4.0
Table 257. IVBR Field Descriptions
5
1
Figure 55. INT Block Diagram
4
1
IVB_ADDR[7:0]
Description
3
1
Interrupt
Requests
2
1
Wake-up
CPU
IVBR
Address
Vector
1
1
0
1
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