MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 276

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.39.2.3
This pin is used to output the select signal from the SPI module to another peripheral with which a data transfer is to take place
when it is configured as a master and it is used as an input to receive the slave select signal when the SPI is configured as slave.
4.39.2.4
In master mode, this is the synchronous output clock. In slave mode, this is the synchronous input clock.
4.39.3
This section provides a detailed description of address space and registers used by the SPI.
4.39.3.1
The memory map for the SPI is given in
address offset. The base address is defined at the SoC level and the address offset is defined at the module level. Reads from
the reserved bits return zeros and writes to the reserved bits have no effect.
4.39.3.2
This section consists of register descriptions in address order. Each description includes a standard register diagram with an
associated figure number. Details of register bit and field function follow the register diagrams, in bit order.
Freescale Semiconductor
Reserved
Reserved
Register
SPIDRH
SPICR1
SPICR2
SPIDRL
SPIBR
SPISR
Name
Memory Map and Register Definition
SS — Slave Select Pin
SCK — Serial Clock Pin
Module Memory Map
Register Descriptions
W
W
W
W
W
W
W
W
R
R
R
R
R
R
R
R
SPIE
SPIF
Bit 7
R15
T15
R7
T7
0
0
SPPR2
XFRW
SPE
R14
T14
R6
T6
6
0
Figure
MM912_634 Advance Information, Rev. 4.0
Table 387. SPI Register Summary
= Unimplemented or Reserved
387. The address listed for each register is the sum of a base address and an
SPPR1
SPTEF
SPTIE
R13
T13
R5
T5
5
0
MODFEN
SPPR0
MODF
MSTR
R12
T12
R4
T4
4
BIDIROE
CPOL
R11
T11
R3
T3
3
0
0
CPHA
SPR2
R10
T10
R2
T2
2
0
0
SPISWAI
SSOE
SPR1
R9
R1
T9
T1
1
0
LSBFE
SPC0
SPR0
Bit 0
R8
T8
R0
T0
0
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