MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 154

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.27.4
The part ID is located in two 8-bit registers PARTIDH and PARTIDL (addresses 0x001A and 0x001B). The read-only value is a
unique part ID for each revision of the chip.
The Version ID in
internal NVM controller.
4.27.5
For the system clock description please refer to
4.27.6
The MCU can operate in different modes. These are described in
can operate in different power modes to facilitate power saving when full system performance is not required. These are
described in
module status whilst the background debug module is active to facilitate debugging.
4.27.6.1
The different modes and the security state of the MCU affect the debug features (enabled or disabled).
The operating mode out of reset is determined by the state of the MODC signal during reset (see
the MODE register shows the current operating mode and provides limited mode switching during operation. The state of the
MODC signal is latched into this bit on the rising edge of RESET.
4.27.6.1.1
This mode is intended for normal device operation. The opcode from the on-chip memory is being executed after reset (requires
the reset vector to be programmed correctly). The processor program is executed from internal memory.
4.27.6.1.2
This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The background debug
module BDM is active in this mode. The CPU executes a monitor program located in an on-chip ROM. BDM firmware waits for
additional serial commands through the BKGD pin.
4.27.6.2
The MM912_634 has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description refer to S12CPMU
section.
4.27.7
The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to
Section 4.31.4.1,
Freescale Semiconductor
Section 4.27.6.2, “Low Power
Part ID Assignments
System Clock Description
Modes of Operation
Security
Note:
143.
Chip Configuration Summary
Low Power Operation
“Security”, and
Table 222
Normal Single-Chip Mode
Special Single-Chip Mode
MC9S12I64
The coding is as follows:
Bit 15-12: Major family identifier
Bit 11-6: Minor family identifier
Bit 5-4: Major mask set revision number including FAB transfers
Bit 3-0: Minor — non full — mask set revision
Device
is a word located in a flash information row. The version ID number indicates a specific version of
Section 4.40.5,
Normal single chip
Special single chip
Mask Set Number
Operation”. Some modules feature a software programmable option to freeze the
Table 222. Assigned Part ID Numbers
Table 222
MM912_634 Advance Information, Rev. 4.0
4.38, “S12 Clock, Reset and Power Management Unit
0N53A
Chip Modes
“Security”.
Table 223. Chip Modes
shows the assigned part ID number and Mask Set number.
Section 4.27.6.1, “Chip Configuration
Part ID
0x38C0
(143)
MODC
1
0
4.33, “Security
MM912_634 - MCU Die Overview
Version ID
0x0000
Table
(S12CPMU)”.
223). The MODC bit in
Summary”. The MCU
(S12X9SECV2)”,
154