MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 266

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Several examples of PLL divider settings are shown in
shortest lock time:
The phase detector inside the PLL compares the feedback clock (FBCLK = VCOCLK/(SYNDIV+1) with the reference clock
(REFCLK = (IRC1M or OSCCLK)/(REFDIV+1)). Correction pulses are generated based on the phase difference between the two
signals. The loop filter alters the DC voltage on the internal filter capacitor, based on the width and direction of the correction
pulse, which leads to a higher or lower VCO frequency.
The user must select the range of the REFCLK frequency (REFFRQ[1:0] bits) and the range of the VCOCLK frequency
(VCOFRQ[1:0] bits) to ensure that the correct PLL loop bandwidth is set.
The lock detector compares the frequencies of the FBCLK and the REFCLK. Therefore the speed of the lock detector is directly
proportional to the reference clock frequency. The circuit determines the lock condition based on this comparison.
If PLL LOCK interrupt requests are enabled, the software can wait for an interrupt request and for instance check the LOCK bit.
If interrupt requests are disabled, software can poll the LOCK bit continuously (during PLL start-up) or at periodic intervals. In
either case, only when the LOCK bit is set, the VCOCLK will have stabilized to the programmed frequency.
4.38.4.2
An example of startup of clock system from Reset is given in
Freescale Semiconductor
4.0 MHz
f
osc
off
off
off
•
•
•
•
•
Use lowest possible f
Use highest possible REFCLK frequency f
The LOCK bit is a read-only indicator of the locked state of the PLL.
The LOCK bit is set when the VCO frequency is within the tolerance, 
out of the tolerance, 
Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling the LOCK bit.
REFDIV[3:0]
System
Reset
LOCK
SYNDIV
POSTDIV $03 (default target f
CPU
PLLCLK
$00
$00
$00
$00
Startup from Reset
Although it is possible to set the dividers to command a very high clock frequency, do not
exceed the specified bus frequency limit for the MCU.
f
VCORST
$1F (default target f
reset state
1.0 MHz
1.0 MHz
1.0 MHz
4.0 MHz
f
REF
768 cycles
VCO
) (
unl
.
REFFRQ[1:0]
/ f
REF
Figure 95. Startup of Clock System After Reset
00
00
00
01
Table 382. Examples of PLL Divider Settings
ratio (SYNDIV value).
PLL
VCO
MM912_634 Advance Information, Rev. 4.0
=f
vector fetch, program execution
=64MHz)
VCO
SYNDIV[5:0]
/4 = 16MHz)
REF
f
$1F
$1F
$0F
$03
PLL
.
Table
increasing
NOTE
382. The following rules help to achieve optimum stability and
t
Figure
lock
64 MHz
64 MHz
32 MHz
32 MHz
f
VCO
95.
VCOFRQ[1:0]
f
PLL
Lock
=16MHz
01
01
00
01
, and is cleared when the VCO frequency is
example change
of POSTDIV
$01
POSTDIV[4:0]
f
PLL
$03
$00
$00
$00
=32 MHz
16 MHz
64 MHz
32 MHz
32 MHz
f
PLL
8.0 MHz
32 MHz
16 MHz
16 MHz
f
bus
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