MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 271

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK cycles long reset
sequence. In case the RESET pin is externally driven low for more than these 768 PLLCLK cycles (External Reset), the internal
reset remains asserted longer.
4.38.5.2.1
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is below the failure assert
frequency f
mode the external oscillator and the clock monitor are disabled.
4.38.5.2.2
The COP (free running watchdog timer) enables the user to check that a program is running and sequencing properly. When the
COP is being used, software is responsible for keeping the COP from timing out. If the COP times out it is an indication that the
software is no longer being executed in the intended sequence; thus COP reset is generated.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the COPOSCSEL bit. In Stop Mode with
PSTP=1 (Pseudo Stop Mode), COPOSCSEL=1 and PCE=1 the COP continues to run, else the COP counter halts in Stop Mode.
Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP register during the selected
time-out period. Once this is done, the COP time-out period is restarted. If the program fails to do this and the COP times out, a
COP reset is generated. Also, if any value other than $55 or $AA is written, a COP reset is generated.
Freescale Semiconductor
CMFA
(256 cycles after release)
Sampled RESET Pin
(see device electrical characteristics for values), the S12CPMU generates a Clock Monitor Reset. In Full Stop
While System Reset is asserted the PLLCLK runs with the frequency f
Clock Monitor Reset
Computer Operating Properly Watchdog (COP) Reset
PLLCLK
RESET
1
1
1
0
Oscillator monitor
fail pending
MM912_634 Advance Information, Rev. 4.0
Table 385. Reset Vector Selection
0
1
0
X
Figure 101. RESET Timing
S12_CPMU drives
RESET pin low
512 cycles
)
NOTE
(
f
VCORST
time out
pending
COP
0
X
1
X
S12_CPMU releases
RESET pin
256 cycles
f
VCORST
)
(
possibly
RESET driven
low
Illegal Address Reset
Illegal Address Reset
Clock Monitor Reset
)
External pin RESET
External pin RESET
VCORST
(
Vector Fetch
COP Reset
POR
POR
LVR
LVR
.
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