MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 111

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Note:
4.16.2.7
This register is actually two separate registers. Reads return the contents of the read-only receive data buffer and writes go to
the write-only transmit data buffer. Reads and writes of this register are also involved in the automatic flag clearing mechanisms
for the SCI status flags.
Offset
100.
Freescale Semiconductor
Note:
Reset
99.
TXINV
W
R
TXDIR
Field
ORIE
NEIE
FEIE
PEIE
(100)
R8
T8
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
7
6
5
4
3
2
1
0
Setting TXINV inverts the TxD output for all cases: data bits, start and stop bits, break, and idle.
(99)
0x47
Ninth Data Bit for Receiver — When the SCI is configured for 9-bit data (M = 1), R8 can be thought of as a ninth receive data
bit to the left of the MSB of the buffered data in the SCID register. When reading 9-bit data, read R8 before reading SCID
because reading SCID completes automatic flag clearing sequences which could allow R8 and SCID to be overwritten with
new data.
Ninth Data Bit for Transmitter — When the SCI is configured for 9-bit data (M = 1), T8 may be thought of as a ninth transmit
data bit to the left of the MSB of the data in the SCID register. When writing 9-bit data, the entire 9-bit value is transferred to
the SCI shift register after SCID is written so T8 should be written (if it needs to change from its previous value) before SCID
is written. If T8 does not need to change in the new value (such as when it is used to generate mark or space parity), it need
not be written each time SCID is written.
TxD Pin Direction in Single-wire Mode — When the SCI is configured for single-wire half-duplex operation
(LOOPS = RSRC = 1), this bit determines the direction of data at the TxD pin.
Transmit Data Inversion — Setting this bit reverses the polarity of the transmitted data output.
Overrun Interrupt Enable — This bit enables the overrun flag (OR) to generate hardware interrupt requests.
Noise Error Interrupt Enable — This bit enables the noise flag (NF) to generate hardware interrupt requests.
Framing Error Interrupt Enable — This bit enables the framing error flag (FE) to generate hardware interrupt requests.
Parity Error Interrupt Enable — This bit enables the parity error flag (PF) to generate hardware interrupt requests.
R7
T7
SCI Data Register (SCID)
7
0
0
1
0
1
0
1
0
1
0
1
0
1
TxD pin is an input in single-wire mode.
TxD pin is an output in single-wire mode.
Transmit data not inverted
Transmit data inverted
OR interrupts disabled (use polling).
Hardware interrupt requested when OR = 1.
NF interrupts disabled (use polling).
Hardware interrupt requested when NF = 1.
FE interrupts disabled (use polling).
Hardware interrupt requested when FE = 1.
PF interrupts disabled (use polling).
Hardware interrupt requested when PF = 1.
R6
T6
6
0
Table 147. SCIC3 Field Descriptions
Table 148. SCI Data Register (SCID)
MM912_634 Advance Information, Rev. 4.0
R5
T5
5
0
R4
T4
4
0
Description
R3
T3
3
0
Serial Communication Interface (S08SCIV4)
R2
T2
0
2
R1
T1
1
0
Access: User read/write
R0
T0
0
0
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