MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 336

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.41.4.5
Read access to the non-blocking window is reserved for future use. When reading from the address window associated with
non-blocking writes, the read returns an all 0s data byte or word. This behavior can change in future revisions.
4.41.4.6
8-bit wide writes or reads are translated into 8-bit wide interface transactions. 16-bit wide, aligned writes or reads are translated
into a16-bit wide interface transactions. 16-bit wide, misaligned writes or reads are split up into two consecutive 8-bit transactions
with the transaction on the odd address first followed by the transaction on the next higher even address. Due to the much more
complex error handling (by the MCU), misaligned 16-bit transfers should be avoided.
4.41.4.7
Since the S12 CPU (as well as the S08) do not provide a method to abort a transfer once started, the D2DI asserts an
D2DERRINT. The ERRIF Flag is set in the D2DSTAT0 register. Depending on the error condition further error flags will be set as
described below. The content of the address and data buffers are frozen and all transactions will be replaced by an IDLE
command, until the error flag is cleared. If an error is detected during the read transaction of a read-modify-write instruction or a
non-blocking write transaction was followed by another write or read transaction, the second transaction is cancelled. The CNCLF
is set in the D2DSTAT0 register to indicate that a transaction has been cancelled. The D2DERRINT handler can read the address
and data buffer register to assess the error situation. Any further transaction will be replaced by IDLE until the ERRIF is cleared.
4.41.4.7.1
If the target detects a wrong command it will not send back an acknowledge. The same situation occurs if the acknowledge is
corrupted. The D2DI detects this missing acknowledge after the timeout period configured in the TIMOUT parameter of the
D2DCTL1 register. In case of a timeout the ERRIF and the TIMEF flags in the D2DSTAT0 register will be set.
4.41.4.7.2
In the final acknowledge cycle of a transaction the target sends two parity bits. If this parity does not match the parity calculated
by the initiator, the ERRIF and the PARF flags in the D2DSTAT0 register will be set. The PAR[1:0] bits contain the parity value
received by the D2DI.
4.41.4.7.3
During the acknowledge cycle the target can signal a target specific error condition. If the D2DI finds the error signal asserted
during a transaction, the ERRIF and the TERRF flags in the D2DSTAT0 register will be set.
4.41.4.8
4.41.4.8.1
In run mode with the D2D Interface enable (D2DEN) bit in the D2D control register 0 clear, the D2DI system is in a low-power,
disabled state. D2D registers remain accessible, but clocks to the core of this module are disabled. On D2D lines the GPIO
function is activated.
4.41.4.8.2
If the CPU enters the STOP mode, any pending transmission is completed. When the D2DCLK output is driven low, clock
generation is stopped. All internal clocks to the D2DCLK are stopped as well, and the module enters a power saving state.
4.41.4.8.3
In case of reset any transaction is immediately stopped and the D2DI module is disabled.
4.41.4.8.4
The D2DI only originates interrupt requests, when D2DI is enabled (D2DIE bit in D2DCTL0 set). There are two different interrupt
requests from the D2D module. The interrupt vector offset and interrupt priority are chip dependent.
Freescale Semiconductor
Non-Blocking Read
Transfer Width
Error Conditions and Handling faults
Low Power Mode Options
Missing Acknowledge
Parity error
Error Signal
D2DI in Run Mode
D2DI in Stop Mode
Reset
Interrupts
MM912_634 Advance Information, Rev. 4.0
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