MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 272

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to the CPMUARMCOP
register to clear the COP timer must occur in the last 25% of the selected time-out period. A premature write will immediately
reset the part.
4.38.5.3
The on-chip POR circuitry detects when the internal supply VDD drops below an appropriate voltage level. The POR is
deasserted, if the internal supply VDD exceeds an appropriate voltage level (voltage levels are not specified in this document
because this internal supply is not visible on device pins).
4.38.5.4
The on-chip LVR circuitry detects when one of the supply voltages VDD, VDDF or VDDX drops below an appropriate voltage
level. If LVR is deasserted the MCU is fully operational at the specified maximum speed. The LVR assert and deassert levels for
the supply voltage VDDX are V
4.38.6
The interrupt/reset vectors requested by the S12CPMU are listed in
addresses and priorities.
4.38.6.1
4.38.6.1.1
The clock source for the RTI is either IRCCLK or OSCCLK depending on the setting of the RTIOSCSEL bit. In Stop mode with
PSTP=1 (Pseudo Stop mode), RTIOSCSEL=1 and PRE=1 the RTI continues to run, else the RTI counter halts in Stop mode.
The RTI can be used to generate hardware interrupts at a fixed periodic rate. If enabled (by setting RTIE=1), this interrupt will
occur at the rate selected by the CPMURTI register. At the end of the RTI timeout period the RTIF flag is set to one and a new
RTI timeout period starts immediately.
A write to the CPMURTI register restarts the RTI timeout period.
4.38.6.1.2
The S12CPMU generates a PLL Lock interrupt when the lock condition (LOCK status bit) of the PLL changes, either from a locked
state to an unlocked state or vice versa. Lock interrupts are locally disabled by setting the LOCKIE bit to zero. The PLL Lock
interrupt flag (LOCKIF) is set to 1 when the lock condition has changed, and is cleared to 0 by writing a 1 to the LOCKIF bit.
4.38.6.1.3
The Adaptive Oscillator Filter contains two different features:
1. Filters spikes of the external oscillator clock.
2. Qualify the external oscillator clock.
When the OSCE bit is 0, then UPOSC stays 0. When OSCE=1 and OSCFILT = 0, then the filter is transparent and no spikes are
filtered. The UPOSC bit is then set after the LOCK bit is set.
Upon detection of a status change (UPOSC), that is an unqualified oscillation becomes qualified or vice versa, the OSCIF flag is
set. Going into Full Stop Mode or disabling the oscillator can also cause a status change of UPOSC.
Freescale Semiconductor
Interrupts
Power-On Reset (POR)
Low-voltage Reset (LVR)
Description of Interrupt Operation
Real Time Interrupt (RTI)
PLL Lock Interrupt
Oscillator Status Interrupt
Autonomous Periodical
Oscillator status interrupt
LVRXA
Low voltage interrupt
RTI timeout interrupt
Interrupt Source
PLL lock interrupt
and V
Interrupt
Table 386. S12CPMU Interrupt Vectors
LVRXD
MM912_634 Advance Information, Rev. 4.0
and are specified in the device Reference Manual.
CCR Mask
I bit
I bit
I bit
I bit
I bit
Table
CPMUAPICTL (APIE)
CPMUINT (LOCKIE)
CPMULVCTL (LVIE)
CPMUINT (OSCIE)
386. Refer to MCU specification for related vector
CPMUINT (RTIE)
Local Enable
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