MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 148

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.26.1.2.4
Freescale Semiconductor
Note:
142.
Offset
SLPBGTR2…0
SLPBG_LOCK
OFFCTR2…0
Reset
SLPBGTRE
OFFCTRE
W
R
CTR3_E
CTR3_2
Field
(142)
Field
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
2-0
6-4
4
3
7
3
2
0xF3
OFFCTRE
ADC offset compensation voltage trim enable bit
ADCOFFC trim - This trim is used to adjust the internal ADC offset compensation voltage
Spare Trim enable bit
Spare Trim bit 2
7
0
Sleep Bandgap trim enable
bg1p25sleep trim lock bit
bg1p25sleep trim - This trim is used to adjust the internal sleep mode 1.25 V bandgap used as a reference for the VDD and
VDDx over-voltage detection.
Trimming Register 3 (CTR3)
0 - no trim can be done
1 - trim can be done by setting OFFCTR[2:0] bits
000: 0%
001: +7.98%
010: +15.97%
011: +23.95%
100: -23.95%
101: -15.97%
110: -7.98%
111: 0%
0 no trim can be done
1 trim lock can be done by setting SLPBGTR[2:0] bits and SLPBG_LOCK bit
000: -12.2% (default)
001: -8.2%
010: -4.2%
011: 0%
100: +4.2%
101: +8.3%
110: +12.5%
111: -12.2% (default)
OFFCTR2
6
0
Table 219. CTR2 - Register Field Descriptions
Table 221. CTR3 - Register Field Descriptions
OFFCTR1
Table 220. Trimming Register 3 (CTR3)
MM912_634 Advance Information, Rev. 4.0
5
0
OFFCTR0
4
0
Description
Description
CTR3_E
3
0
CTR3_2
MM912_634 - Analog Die Trimming
2
0
CTR3_1
1
0
Access: User read/write
CTR3_0
0
0
148