MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 304

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.40.3.2.8
The FERSTAT register reflects the error status of internal Flash operations.
All flags in the FERSTAT register are readable and only writable to clear the flag.
4.40.3.2.9
The FPROT register defines which P-Flash sectors are protected against program and erase operations.
The (unreserved) bits of the FPROT register are writable with the restriction that the size of the protected region can only be
increased.
During the reset sequence, the FPROT register is loaded with the contents of the P-Flash protection byte in the Flash
configuration field at global address 0x3_FF0C located in P-Flash memory (see
. To change the P-Flash protection that will be loaded during the reset sequence, the upper sector of the P-Flash memory must
be unprotected, then the P-Flash protection byte must be reprogrammed. If a double bit fault is detected while reading the
P-Flash phrase containing the P-Flash protection byte during the reset sequence, the FPOPEN bit will be cleared and remaining
bits in the FPROT register will be set to leave the P-Flash memory fully protected.
Trying to alter data in any protected area in the P-Flash memory will result in a protection violation error and the FPVIOL bit will
be set in the FSTAT register. The block erase of a P-Flash block is not possible if any of the P-Flash sectors contained in the
same P-Flash block are protected.
Freescale Semiconductor
Note:
210.
MGSTAT[1:0]
Reset
W
DFDIF
R
SFDIF
Field
RSVD
Field
1–0
1
0
The single bit fault and double bit fault flags are mutually exclusive for parity errors (an ECC fault occurrence can be either single fault
or double fault but never both). A simultaneous access collision (read attempted while command running) is indicated when both SFDIF
and DFDIF flags are high.
2
Double Bit Fault Detect Interrupt Flag — The setting of the DFDIF flag indicates that a double bit fault was detected in the
stored parity and data bits during a Flash array read operation or that a Flash array read operation was attempted on a Flash
block that was under a Flash command operation.
has no effect on DFDIF.
Single Bit Fault Detect Interrupt Flag — With the IGNSF bit in the FCNFG register clear, the SFDIF flag indicates that a
single bit fault was detected in the stored parity and data bits during a Flash array read operation or that a Flash array read
operation was attempted on a Flash block that was under a Flash command operation. The SFDIF flag is cleared by writing a
1 to SFDIF. Writing a 0 to SFDIF has no effect on SFDIF.
7
0
0
Reserved Bit — This bit is reserved and always reads 0
Memory Controller Command Completion Status Flag — One or more MGSTAT flag bits are set if an error is detected
during execution of a Flash command or during the Flash reset sequence. See
Description,” and
Flash Error Status Register (FERSTAT)
P-Flash Protection Register (FPROT)
0
1
0
1
No double bit fault detected
Double bit fault detected or an invalid Flash array read operation attempted
No single bit fault detected
Single bit fault detected and corrected or an invalid Flash array read operation attempted
6
0
0
Section 4.40.6,
= Unimplemented or Reserved
Table 424. Flash Error Status Register (FERSTAT)
Table 423. FSTAT Field Descriptions (continued)
Table 425. FERSTAT Field Descriptions
MM912_634 Advance Information, Rev. 4.0
5
0
0
“Initialization” for details.
(210)
4
0
0
The DFDIF flag is cleared by writing a 1 to DFDIF. Writing a 0 to DFDIF
Description
Description
.
3
0
0
Table
404) as indicated by reset condition ‘F’ in
Section 4.40.4.5, “Flash Command
2
0
0
DFDIF
1
0
SFDIF
0
0
304