MM912H634CV1AE Freescale Semiconductor, MM912H634CV1AE Datasheet - Page 71

• Manufacturer Part Number: MM912H634CV1AE
• Description: 64KS12 LIN2xLS/HS Isense
• Manufacturer: Freescale Semiconductor
• Series: -r

Specifications of MM912H634CV1AE

• Applications: Automotive
• Core Processor: HCS12
• Program Memory Type: FLASH (64 kB)
• Controller Series: HCS12
• Ram Size: 6K x 8
• Interface: LIN
• Number Of I /o: -
• Voltage - Supply: 5.5 V ~ 27 V
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP Exposed Pad
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4.9
To wake-up the MM912_634 analog die from Stop or Sleep mode, several wake-up sources are implemented. As
described in
the MCU combined with a transition to Normal mode. A wake-up from Sleep mode will result in a transition to
Reset mode. In any case, the source of the wake-up can be identified by reading the Wake-up Source Register
(WSR). The Wake-up Source Register (WSR) has to be read after a wake-up condition in order to execute a new STOP mode
command. Two base clock cycles (f
In general, there are the following seven main wake-up sources:
4.9.1
4.9.1.1
Any state digital change on a Wake-up Enabled Lx input will issue a wake-up. In order to select and activate a Wake-up Input
(Lx), the Wake-up Control Register (WCR) must be configured with appropriate LxWE inputs enabled or disabled before entering
low power mode. The Lx - Wake-up may be combined with the Forced Wake-up.
Note: Selecting a Lx Input for wake-up will disable a selected analog input once entering low power mode.
4.9.1.2
To reduce external power consumption during low power mode a cyclic wake-up has been implemented. Configuring the Timing
Control Register (TCR) a specific cycle time can be selected to implement a periodic switching of the HS1 or HS2 output with the
corresponding detection of an Lx state change. Any configuration of the HSx in the High Side Control Register (HSCR) will be
ignored when entering low power mode. The Lx - Cyclic Sense Wake-up may be combined with the Forced Wake-up. In case
both (forced and Lx change) events are present at the same time, the Forced Wake-up will be indicated as Wake-up source.
Freescale Semiconductor
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Wake-up by a state change of one of the Lx inputs
Wake-up by a state change of one of the Lx inputs during a cyclic sense
Wake-up due to a forced wake-up
Wake-up by the LIN module
Wake-up by D2D interface (Stop mode only)
Wake-up due to internal / external Reset (Stop mode only)
Wake-up due to loss of supply voltage (Sleep mode only)
Wake-up / Cyclic Sense
Section 4.4, “Modes of
Wake-up Sources
Lx - Wake-up (Cyclic Sense Disabled)
Lx - Cyclic Sense Wake-up
Once Cyclic Sense is configured (CSSEL!=0), the state change is only recognized from one
cyclic sense event to the next.
The additional accuracy of the cyclic sense cycle by the WD clock trimming is only active
during STOP mode. There is no trimmed clock available during SLEEP mode.
D2DCLK
D2DINT
D2D3
D2D2
D2D1
D2D0
Wake Up
D2D
BASE
Operation, a wake-up from Stop mode will result in an interrupt (D2DINT) to
Wake Up
Module
) delay are required between the WSR read and MCR write.
MM912_634 Advance Information, Rev. 4.0
Figure 19. Wake-up Sources
Wake Up
Forced
LIN Wake Up
Lx – Wake Up
Cyclic Wake Up
Cyclic Sense / Forced
NOTE
Wake Up Timer
HS1
HS2
LIN
L0
L1
L2
L3
L4
L5
Wake-up / Cyclic Sense
LIN Bus
V
SUP
MCU
ANALOG
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